# Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

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• ### Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Publication Year: 1999
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Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the ori... View full abstract»

• ### Author index

Publication Year: 1999, Page(s): 302
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• ### Supplementary symmetrical logic circuit structure

Publication Year: 1999, Page(s):42 - 47
Cited by:  Papers (5)
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The Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) is a fully active, self sustaining architecture intended primarily for the design and fabrication of logic synthesizing circuits with a radix greater than two. Any r'-valued logic function of n'-places (where: r' is the radix and an integer greater than I, and n' is an integer greater than 0) can be implemented with the SUS-LOC st... View full abstract»

• ### “New lamps for old!” (generalized multiple-valued neurons)

Publication Year: 1999, Page(s):36 - 41
Cited by:  Papers (3)
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Contributions to multiple-valued threshold logic in the seventies are reviewed at the light of developments in the area of artificial neural networks. It is shown that it is possible to adapt methods of design of feedforward neural networks to generate networks of multiple-valued neurons to realize any multiple-valued function View full abstract»

• ### Multiple-valued content-addressable memory using metal-ferroelectric-semiconductor FETs

Publication Year: 1999, Page(s):30 - 35
Cited by:  Papers (5)
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This paper presents a design of a non-volatile multiple-valued content-addressable memory (MVCAM) using metal-ferroelectric-semiconductor (MFS) FETs. An MFSFET is an important device with a non-destructive read scheme. Multiple-valued stored data are directly represented by remnant polarization states that correspond to threshold voltages of an MFSFET. Since one-digit comparison between multiple-v... View full abstract»

• ### On axiomatization of conditional entropy of functions between finite sets

Publication Year: 1999, Page(s):24 - 28
Cited by:  Papers (3)
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In this paper we present a new axiomatization of the notion of entropy of functions between finite sets and we introduce and axiomatize the notion of conditional entropy between functions. The results can be directly applied to logic functions, which can be regarded as functions between finite sets. Our axiomatizations are based on properties of entropy with regard to operations commonly applied t... View full abstract»

• ### Quaternion groups versus dyadic groups in representations and processing of switching functions

Publication Year: 1999, Page(s):18 - 23
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In this paper we compare effects of two different domain groups for switching functions to the efficiency of calculation of spectral transforms (ST) representations and the complexity of Decision diagrams (DDs) representations. Dyadic groups and quaternion groups are assumed for domain groups for switching functions. We compared space and time complexity in calculation of STs representations throu... View full abstract»

• ### Representation theorems and theorem proving in non-classical logics

Publication Year: 1999, Page(s):242 - 247
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In this paper we present a method for automated theorem proving in non-classical logics having as algebraic models bounded distributive lattices with certain types of operators. The idea is to use a Priestley-style representation for distributive lattices with operators in order to define a class of Kripke-style models with respect to which the logic is sound and complete. If this class of Kripke-... View full abstract»

• ### Multivalued binary relations and Post algebras

Publication Year: 1999, Page(s):10 - 17
Cited by:  Papers (1)
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This paper deals with a multivalued extension of the concept of a binary relation on a set E. If R is such an r-valued relation on E, far every (x, y)∈E2, there exists exactly one i∈{0, 1, ..., r-1} such that the degree of comparability of (x, y) with respect to R is equal to i. The set of all r-valued relations on E is then equipped with an order relation ⩽ and turns out ... View full abstract»

• ### Probabilistic and truth-functional many-valued logic programming

Publication Year: 1999, Page(s):236 - 241
Cited by:  Papers (4)
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We introduce probabilistic many-valued logic programs in which the implication connective is interpreted as material implication. We show that probabilistic many-valued logic programming is computationally more complex than classical logic programming. More precisely, some deduction problems that are P-complete for classical logic programs are shown to be co-NP-complete for probabilistic many-valu... View full abstract»

• ### On the concept of qualitative fuzzy set

Publication Year: 1999, Page(s):282 - 287
Cited by:  Papers (9)
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Following T.Y. LIN vague concepts such as “high” or “small” (“amount of money” as linguistic variable) should be described by classes of “equivalent” fuzzy sets on a fixed suitable universe U. Furthermore LIN proposed to generate such classes by factorization of the fuzzy power set FP(U) of U with respect to a given equivalence relation ≈ on FP(U)... View full abstract»

• ### Development of quantum functional devices for multiple-valued logic circuits

Publication Year: 1999, Page(s):2 - 9
Cited by:  Papers (8)
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Quantum functional devices exhibiting unique current-voltage characteristics are reported for the application of multiple-valued logic circuits. Multiple negative-differential-resistance (NDR) characteristics in drain current-voltage characteristics are demonstrated by using multiple-junction surface tunnel transistors (MJ-STTs). Some multiple-valued logic gates such as inverter and literal are im... View full abstract»

• ### Information relationships and measures in application to logic design

Publication Year: 1999, Page(s):228 - 235
Cited by:  Papers (7)
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In this paper, the theory of information relationships and relationship measures is considered and its application to logic design is discussed. This theory makes operational the famous theory of partitions and set systems of Hartmanis. The information relationships and measures enable us to analyze relationships between the modeled information streams and constitute an important analysis apparatu... View full abstract»

• ### B-ternary logic based asynchronous micropipeline

Publication Year: 1999, Page(s):214 - 219
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In this paper, a B-ternary logic based asynchronous pipeline is presented. The pipeline processes binary dates elastically. It has high speed operation potential an spite of having an idle phase, because the stages of the pipeline operate concurrently. The mechanism for correct pipeline behavior and the designed circuits are provided View full abstract»

• ### Redundant complex arithmetic and its application to complex multiplier design

Publication Year: 1999, Page(s):200 - 207
Cited by:  Papers (3)
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This paper presents a class of complex number representations called Redundant Complex Number Systems (RCNSs), which are useful for designing VLSI signal processors with complex arithmetic capability. A redundant complex: number system is defined as an imaginary-radix number system having a redundant integer digit set. This makes possible the construction of high-speed complex arithmetic circuits:... View full abstract»

• ### Arithmetic circuits for analog digits

Publication Year: 1999, Page(s):186 - 191
Cited by:  Papers (9)
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The Overlap Resolution Number System (ORNS) employs bit level analog residue arithmetic, and opens up a powerful approach to digital computing. This new redundant representation of signals, with Continuous Valued Digits, presents new methods for binary arithmetic and digital signal processing. The number system is based on analog residue digits, as opposed to binary or multiple-valued digit levels... View full abstract»

• ### Ternary multiplication circuits using 4-input adder cells and carry look-ahead

Publication Year: 1999, Page(s):174 - 179
Cited by:  Papers (3)
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We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multipliers. ... View full abstract»

• ### Matrix-valued EXOR-TDDs in decomposition of switching functions

Publication Year: 1999, Page(s):154 - 159
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EXOR Ternary Decision Diagrams (EXOR-TDD's) proved useful in several applications in logic design. This paper shows that EXOR-TDDs are also useful in functional decomposition. We prove that checking simple disjoint decomposition of f with respect to a subset of r variables is equivalent to building the EXOR-TDD for a matrix-valued function of (n-r) variables. Transferring the problem of decomposit... View full abstract»

• ### Self-checking multiple-valued circuit based on dual-rail current-mode differential logic

Publication Year: 1999, Page(s):275 - 279
Cited by:  Papers (1)
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A multiple-valued current-mode (MVCM) circuit based on dual-rail differential logic has been proposed for high-speed arithmetic systems at a low supply voltage. This paper presents a new totally self-checking circuit based on dual-rail MVCM logic, where almost all the basic components except a differential-pair circuit have been already duplicated which results in small hardware overhead compared ... View full abstract»

• ### The number of cascade functions

Publication Year: 1999, Page(s):131 - 135
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Cascade function is a Boolean function which can be implemented by a so-called cascade network. An n input cascade network is a circuit built with n-1 two-input-one-output gates (i.e., dyadic operations) such that at least one input of each gate is a network input. By arranging the inputs in a proper order these networks can be presented in a “cascade” shape, which is the origin of the... View full abstract»

• ### Multiple-valued minimization to optimize PLAs with output EXOR gates

Publication Year: 1999, Page(s):99 - 104
Cited by:  Papers (10)
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This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. We conjecture that, when n is sufficien... View full abstract»

• ### Bi-decompositions of multi-valued functions for circuit design and data mining applications

Publication Year: 1999, Page(s):50 - 58
Cited by:  Papers (4)
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We present efficient algorithms for the bi-decomposition of arbitrary incompletely specified functions in variable-valued logic. Several special cases are discussed. The algorithms are especially applicable for Data Mining applications, because, in contrast to the general multi-valued approaches to function decomposition that decompose to arbitrary tables, we create a network from multi-valued two... View full abstract»

• ### Transformations between signed and classical clause logic

Publication Year: 1999, Page(s):248 - 255
Cited by:  Papers (11)
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In the last years two automated reasoning techniques for clause normal form arose in which the use of labels are prominently featured: signed logic and annotated logic programming, which can be embedded into the first. The underlying basic idea is to generalise the classical notion of a literal by adorning an atomic formula with a sign or label which in general consists of a possibly ordered set o... View full abstract»

• ### On some classes of fuzzy information granularity and their representations

Publication Year: 1999, Page(s):288 - 293
Cited by:  Papers (4)
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This paper describes some classes of fuzzy information granularity and their representation methods. Fuzzy information granularity introduced by Zadeh is that “granularity relates to clumpiness of structure, while granulation refers to partitioning an object into a collection of granules, with a granule being a clump of objects (points) drawn together by indistinguishability, similarity, pro... View full abstract»

• ### State assignment techniques in multiple-valued logic

Publication Year: 1999, Page(s):220 - 225
Cited by:  Papers (6)
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Multiple-Valued Logic (MVL) functions are implemented via Boolean multiple-wire arrangements where a careful state assignment methodology is used to ensure efficient implementation regimes. A `power of N' module is proposed for GF (23). The method avoids the need to factorize the polynomial and circuits can be realised using a combination of NOT AND and XOR functions. In addition, a nov... View full abstract»