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22nd International Conference on Field Programmable Logic and Applications (FPL)

29-31 Aug. 2012

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  • Index

    Publication Year: 2012, Page(s):754 - 758
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    Publication Year: 2012, Page(s):1 - 4
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  • [Front cover]

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  • DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS

    Publication Year: 2012, Page(s):394 - 399
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (578 KB) | HTML iconHTML

    Networks-on-FPGA consist of a network of switches connected with point-to-point links and can cover sufficiently the communication needs of complex systems implemented on FPGA platforms. The efficient implementation of such networks requires the appropriate tuning of their components to the characteristics of the FPGA's logic and memory resources. In this paper, we present a distributed switch arc... View full abstract»

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  • An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay

    Publication Year: 2012, Page(s):400 - 406
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1235 KB) | HTML iconHTML

    With the increasing number of processors in Multiprocessor System-on-Chips (MPSoCs), Network-on-Chips (NoCs) are replacing conventional buses as the interprocessor communication architecture. Since different use cases might be running on MPSoCs, there is a need for dynamically reconfigurable NoC. However, most dynamically reconfigurable NoCs have a large area overhead due to the additional reconfi... View full abstract»

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  • An acceleration of a graph cut segmentation with FPGA

    Publication Year: 2012, Page(s):407 - 413
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1496 KB) | HTML iconHTML

    Image segmentation is one of the most important steps in image processing. The graph cut is an effective method for the image segmentation. For calculating the graph cut, the max-flow algorithm is widely used, but it requires long computation time. To execute the graph cut in real-time, the acceleration of max-flow algorithm with hardware is necessary. In this paper, we propose an implementation o... View full abstract»

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  • An FPGA acceleration of a level set segmentation method

    Publication Year: 2012, Page(s):414 - 420
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2161 KB) | HTML iconHTML

    Image segmentation is one of the most important tasks in the image processing. The level set method is a powerful algorithm for the segmentation. In the level set method, a three-dimensional auxiliary function is used for detecting objects of various shapes. Its computational complexity is, however, very high, and many techniques have been proposed to reduce the computational complexity. In this p... View full abstract»

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  • A high performance, open source SATA2 core

    Publication Year: 2012, Page(s):421 - 428
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB) | HTML iconHTML

    This paper describes the design and implementation of an open source FPGA-based SATA2 core. It provides the ability to directly interface with hardware cores which is beneficial for high performance and embedded computing applications. Additionally, the core has a bus interface and DMA engine that makes it available to the operating system through a Linux block device driver. Measurements with sol... View full abstract»

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  • IP-XACT extensions for IP interoperability guarantees and software model generation

    Publication Year: 2012, Page(s):429 - 436
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (399 KB) | HTML iconHTML

    This paper presents a set of novel metadata extensions that are used to specify the interfaces on Xilinx IP cores and their software models under a uniform data model which allows enhanced design rule checking in the system design process. We also present a suite of tools which can be used to generate executable software simulation models of complete systems from their specifications under that da... View full abstract»

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  • K-means implementation on FPGA for high-dimensional data using triangle inequality

    Publication Year: 2012, Page(s):437 - 442
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB) | HTML iconHTML

    One of the challenges to data mining raised by technology development is that both data size and dimensionality is growing rapidly. K-means, one of the most popular clustering algorithms in data mining, suffers in computational time when used for large data sets and data with high dimensionality. In this paper, we propose a hardware architecture for K-means with triangle inequality optimization on... View full abstract»

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  • Enhancing performance of Tall-Skinny QR factorization using FPGAs

    Publication Year: 2012, Page(s):443 - 450
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (937 KB) | HTML iconHTML

    Communication-avoiding linear algebra algorithms with low communication latency and high memory bandwidth requirements like Tall-Skinny QR factorization (TSQR) are highly appropriate for acceleration using FPGAs. TSQR parallelizes QR factorization of tall-skinny matrices in a divide-and-conquer fashion by decomposing them into sub-matrices, performing local QR factorizations and then merging the i... View full abstract»

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  • Real-time corner and polygon detection system on FPGA

    Publication Year: 2012, Page(s):451 - 457
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1935 KB) | HTML iconHTML

    Corner detection is a fundamental step in the image recognition. In this paper, we propose a new corner detection algorithm based on the circumferential distribution of the edges around each pixel. The computational complexity of this algorithm is high, but this algorithm is suitable for hardware implementation, and we can achieve high performance on an FPGA. Furthermore, this algorithm can detect... View full abstract»

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  • Deep-pipelined FPGA implementation of ellipse estimation for eye tracking

    Publication Year: 2012, Page(s):458 - 463
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1416 KB) | HTML iconHTML

    This paper presents a deep-pipelined FPGA implementation of real-time ellipse estimation for eye tracking. The system is constructed by the Starburst algorithm on a stream-oriented architecture and the RANSAC algorithm without any external memories. In particular, the paper presents comparative results between three different hypothesis generators for the RANSAC algorithm based on Cramer's rule, G... View full abstract»

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  • A Benign Hardware Trojan on FPGA-based embedded systems

    Publication Year: 2012, Page(s):464 - 470
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (617 KB) | HTML iconHTML

    In this paper we present the use of Benign Hardware Trojans (BHT) as a security measure for an embedded system with a software component and a hardware execution environment. Based on delay logic, process variation, and selective transistor aging, the BHT can be incorporated into an embedded system for the software and the hardware components to authenticate each other before functional execution.... View full abstract»

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  • Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS

    Publication Year: 2012, Page(s):747 - 753
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (375 KB) | HTML iconHTML

    A5 is the basic cryptographic algorithm used in GSM cell-phones to ensure that the user communication is protected against illicit acts. The A5/1 version was developed in 1987 and has since been under attack. The most recent attack on A5/1 is the “A51 security project”, led by Karsten Nohl that consists of the creation of rainbow tables that map the internal state of the algorithm wi... View full abstract»

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  • On reconfigurable fabrics and generic side-channel countermeasures

    Publication Year: 2012, Page(s):663 - 666
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (657 KB) | HTML iconHTML

    The use of field programmable devices in security-critical applications is growing in popularity; in part, this can be attributed to their potential for balancing metrics such as efficiency and algorithm agility. However, in common with non-programmable alternatives, physical attack techniques such as fault and power analysis are a threat. We investigate a family of next-generation field programma... View full abstract»

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