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Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Date 19-19 May 1999

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  • Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

    Publication Year: 1999
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    Freely Available from IEEE
  • Author index

    Publication Year: 1999 , Page(s): 0_24 - 0_27
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    Freely Available from IEEE
  • A wideband quadrature LO generator in digital CMOS

    Publication Year: 1999 , Page(s): 657 - 659
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    A quadrature local oscillator (LO) generator using only CMOS transistors produces quadrature outputs with a phase error of less than 2 degrees over 200 MHz to 950 MHz from a single phase input. The circuit uses a novel multiple-stage topology with inverters as phase delay elements. View full abstract»

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  • A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution

    Publication Year: 1999 , Page(s): 605 - 608
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    A novel cyclic time-to-digital converter (TDC) is proposed in this paper. The measured resolution (or LSB width equivalent) can reach 68 picoseconds, and the corresponding single-shot errors are around 1/2 LSB width. Under a single 3.3 V power supply, the stand-by current consumption is measured to be 0.3 mA only, including the I/O pads. The operation current consumption is measured to be 370 uA under 100 k/sec measurement rate View full abstract»

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  • A 2 Vpp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF

    Publication Year: 1999 , Page(s): 509 - 512
    Cited by:  Papers (6)
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    A fully balanced (FB) transconductor using two multi-input single-ended CMOS transconductors is proposed. The FB transconductor achieves a 2Vpp linear input range at 2.5 V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with linear input-range of 1.2 Vpp and at 1.6 V with linear input-range of 0.9 Vpp. A 2.5 V 2.5 MHz FB Gm-C filter using the FB transconductors achieves a CMRR of 45 dB and a passband IIP3 of 32 dBm View full abstract»

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  • A next generation architecture optimized for high density system level integration

    Publication Year: 1999 , Page(s): 175 - 178
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    Altera has developed a next generation architecture called APEX TM to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system. This new architecture will support a family of devices exceeding 2 million gates in density. Density and speed improvements are achieved through an enhanced hierarchical routing structure View full abstract»

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  • OwL: An interface description language for IP reuse

    Publication Year: 1999 , Page(s): 403 - 406
    Cited by:  Papers (3)  |  Patents (2)
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    A new language for interface description, named OwL, and its applications are proposed. The purpose of OwL is to reuse IPs. By specifying the functionality of the IP as an interface protocol, the IP can be used as a blackbox. The full interface specification of an SDRAM, including refresh control, is represented by 205 lines of OwL description. Two applications of Ow L are also described. The first application is a waveform generator for the on-line manual. The second application is a means of checking the connectability of two IPs View full abstract»

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  • Testing analog circuits by supply voltage variation and supply current monitoring

    Publication Year: 1999 , Page(s): 155 - 158
    Cited by:  Papers (3)
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    A technique for sensitizing faults in analog circuits by varying the supply voltage and monitoring the supply current is discussed. The detection of short circuit faults is demonstrated with a simple CMOS circuit. The technique is applied to a larger analog circuit and significantly improved fault cover is obtained View full abstract»

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  • Frequency scalable non-linear waveform generator for mixed-signal power-factor-correction IC controller

    Publication Year: 1999 , Page(s): 609 - 612
    Cited by:  Papers (1)
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    This paper derives a family of digital non-linear waveform generators fundamental to the development of an adaptive mixed-signal IC controller for power-factor-correction (PFC) of high-frequency switching AC-to-DC converters with the objective of significantly lowering the cost of rectifier design. The controller application is described along with combined controller and power stage simulation results. Simple hardware implementations of digital waveform generators are derived and verified with experimental results from a 1.2 μ CMOS test chip View full abstract»

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  • A Si/SiGe HBT timing generator IC for high-bandwidth impulse radio applications

    Publication Year: 1999 , Page(s): 221 - 224
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    A precise timing generator is presented which forms the heart of a wideband impulse radio or radar system. The circuit is implemented in a 45 GHz Si/SiGe HBT technology, and can produce a pulse inside a 100 ns window with an accuracy of 2 ps and a jitter of less than 10 ps. The integrated circuit contains a mixture of analog, digital, and RF functions, consumes 0.5 W, and operates at a clock rate of up to 2.5 GHz View full abstract»

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  • A 4-dB NF GPS receiver front-end with AGC and 2-b A/D

    Publication Year: 1999 , Page(s): 205 - 208
    Cited by:  Papers (7)
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    A dual-IF GPS receiver front-end integrates all the active circuitry to down-convert, amplify and digitize the 1,575.42 GHz L1 signal. The chip includes 3 dB NF LNA, 38 dB image reject mixer, VCO with integrated LC tank and varactor, PLL synthesizer, 55-dB range AGC with charge-pump control, 2-b A/D, crystal oscillator and TTL-compatible buffers. The receiver noise figure is 4 dB and maximum gain is 120 dB with a power consumption of 49 mA at 3 V supply. The AGC and 2-b A/D offer better SNR and significantly better blocking performance than the commonly used 1-b quantizers View full abstract»

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  • RF transmitter architectures and circuits

    Publication Year: 1999 , Page(s): 197 - 204
    Cited by:  Papers (23)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    This paper describes the design of RF transmitters for wireless applications. Following a review of constant- and variable-envelope modulation, general issues regarding the baseband/RF interface and the power amplifier/antenna interface are introduced. Various transmitter architectures are then presented and the design of upconversion mixers and power amplifiers is studied. Examples of state of the art are also described View full abstract»

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  • A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming

    Publication Year: 1999 , Page(s): 187 - 190
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    A high density, Programmable Logic Device (PLD) family developed for hot socketing and high performance is discussed. The family is fabricated on a 0.32 um quadruple layer metal process. The largest family member is a 512 macrocell part with typical pin to pin delays of 4.9 ns. The design techniques and testing methodology to guarantee safe hot socketing are described. Streamlined In System Programming (ISP) and circuits used to configure EEPROM cells with a 3.3-V supply are also discussed View full abstract»

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  • A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications

    Publication Year: 1999 , Page(s): 649 - 652
    Cited by:  Papers (17)
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    A VCO and a prescaler designed for wireless applications with very low power consumption requirements are presented. The VCO has a phase noise of -111 dBc/Hz at 100 kHz offset from a 1 GHz carrier and a tuning range of 18% while consuming only 250 μA from a 2.5 V supply. The 64/65 dual modulus prescaler operates at the same frequency with only 0.9 mW. Both circuits are integrated in 0.25 μm standard CMOS View full abstract»

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  • Design of high-Q varactors for low-power wireless applications using a standard CMOS process

    Publication Year: 1999 , Page(s): 641 - 644
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    The power consumption of an LC-tank oscillator is strongly affected by the varactor quality factor, whether the inductor is on- or off-chip. This paper proposes a new solution to realize high-Q, highly tunable on-chip varactors in a standard CMOS process, achieving a quality factor higher than 100 at 1 GHz, for a tuning ratio of 2. Other solutions are described and their respective advantages compared, while their characteristics are measured for a 0.5 μm process View full abstract»

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  • A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reload

    Publication Year: 1999 , Page(s): 235 - 238
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    This paper describes the key circuit features of the 32 KB data cache memory embedded in the first AltiVecTM enhanced PowerPC TM microprocessor. The memory array implements a castout/reload scheme that allows both a read and a write operation within a single machine cycle which greatly increases cache bandwidth. A newly implemented vector alignment multiplexer supports the additional vector instructions. The design incorporates self-resetting and dynamic circuit techniques to achieve a cycle time of less than 2.0 ns fabricated in a 1.8-volt, 0.2 μm, 6-layer copper CMOS process View full abstract»

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  • Including inductive effects in interconnect timing analysis

    Publication Year: 1999 , Page(s): 445 - 452
    Cited by:  Papers (21)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    Including inductive effects in interconnect timing analysis has become increasingly important in today's deep submicron designs. In this tutorial paper we will describe the technology trends that brought us to this juncture, summarize when inductance should be included, and consider some of the extraction and modeling techniques available. This coverage will not be an exhaustive summary of all the extraction and analysis techniques available, but one that is primarily focused on extraction methods that efficiently capture frequency dependence due to proximity effects and moment-based analysis techniques View full abstract»

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  • Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs

    Publication Year: 1999 , Page(s): 231 - 234
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    New multiple twisted data line techniques to reduce both bit line (BL) and word line (WL) coupling noises in scaled embedded DRAMs are proposed and analyzed. An improved noise/signal ratio resulting from the application of the proposed techniques is confirmed by soft-error rate measurements on test chips with 256-Mbit and 1-Gbit level integration. At the 256-Mbit level, when the proposed techniques are applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional twisted Bl (TBL) and WL schemes View full abstract»

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  • Single GSM mixed signal superchip with 96k bytes FLASH and low power micro-controller

    Publication Year: 1999 , Page(s): 103 - 106
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    We developed a single mixed signal baseband chip performing all the necessary signal processing required for cellular phone communication in Global Systems for Mobile Communication (GSM) cellular terminals. The chip is a total GSM baseband solution consisting of voice codec, data converters, 100 MHz DSP, low power micro-controller, and ASIC. The device contains a 48k-word (16 bit) programmable instruction FLASH, an 8k-word Dual-Port Random Access Memory (DPRAM) for the data and instruction cache, and 4k-Bytes SRAM for the micro-controller. The chip size is 10.6×10.0 mm2 including approximately 2.6M transistors and about 5000 analog components implemented in 0.35 μm 3 V linear FLASH CMOS technology View full abstract»

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  • A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider

    Publication Year: 1999 , Page(s): 517 - 520
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    A voltage controlled differential injection locked frequency divider (VCDILFD) with a large locking range is designed in a 0.24 μm CMOS technology. A 29% locking range is achieved by an optimal inductor design and also by employing high Q accumulation mode MOS varactors to change the free-running oscillation frequency of the divider. The measurement results show frequency division at 5 GHz, with more than 1 GHz locking range and power consumption of less than 1 mW View full abstract»

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  • Oscillator phase noise: a tutorial

    Publication Year: 1999 , Page(s): 373 - 380
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    An understanding of how device noise becomes phase noise in practical oscillators is complicated by the presence of nonlinearities (for amplitude stabilization), and by the failure of time invariance. This tutorial reviews the qualitative insights of older (linear, time-invariant) models, and supplements those with powerful additional insights provided by a recently developed time-varying model. Among the most significant are the importance of symmetry in suppressing the upconversion of 1/f noise into noise near the carrier, and an appreciation of cyclostationary effects View full abstract»

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  • Analog sense amplifiers for high density NOR flash memories

    Publication Year: 1999 , Page(s): 247 - 250
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    Three different types of analog sense amplifiers (ASA) are presented that offer the precision needed for the storage of up to 6b/cell in standard NOR flash memories for embedded mass storage applications. Three test chips with 1 Mcells array have been integrated in a 3 V 0.5 μm common-ground double metal double poly standard NOR flash-EEPROM technology for embedded memory to validate the circuits View full abstract»

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  • The challenge of designing global signals in UDSM CMOS

    Publication Year: 1999 , Page(s): 429 - 435
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    This paper describes several of the challenges facing designers of global signals in high-performance, ultra-deep submicron (UDSM) CMOS designs. Practical guidelines and a building block approach are presented to solve or avoid problems with global signals as the technology shrinks to 0.25 micron and below. Power distribution is also treated as a global signal. Guidelines are presented for estimation, planning and implementation of global signals. The objective is to present a methodology that will provide a sound foundation for building systems-on-a-chip and resolve methodology and modeling issues early in the design cycle View full abstract»

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  • A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications

    Publication Year: 1999 , Page(s): 597 - 600
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A high-speed dual-modulus prescaler has been developed in 0.36 μm CMOS. The prescaler was designed for low-power frequency synthesizers for 900 MHz to 1.9 GHz wireless applications. It provides programmable division ratio of 64, 65, 128, and 129. Power consumption was 2.9 mW with 1.9 GHz input frequency and 3.3 V power supply. The measured residual phase noises were -142 dBc/Hz at 100 Hz offset and -166 dBc/Hz at 100 kHz offset View full abstract»

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  • Clock verification in the presence of IR-drop in the power distribution network

    Publication Year: 1999 , Page(s): 437 - 440
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    Clock nets are the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of the clock signal directly impacts the performance of a VLSI chip. Clock verification requires high accuracy and is typically performed using circuit simulators. In high-performance deep-submicron digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher load on the power distribution network with the potential of substantial IR-drop. However, as IR-drop is a full-chip phenomenon, circuit simulation is extremely time consuming. In this paper, we present a loosely coupled iterative technique for clock verification in the presence of full-chip dynamic IR-drop. The degradation in the clock signal due to dynamic IR-drop is demonstrated on a small example as well as upon a large chip. In addition, we also discuss risks associated with assuming a static IR-drop budget upon clock propagation View full abstract»

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