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Embedded and Real-Time Computing Systems and Applications (RTCSA), 2012 IEEE 18th International Conference on

Date 19-22 Aug. 2012

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Displaying Results 1 - 25 of 72
  • [Cover art]

    Publication Year: 2012 , Page(s): C4
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  • [Title page i]

    Publication Year: 2012 , Page(s): i
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  • [Title page iii]

    Publication Year: 2012 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2012 , Page(s): iv
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  • Table of contents

    Publication Year: 2012 , Page(s): v - x
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  • Message from the RTCSA 2012 Conference Chairs

    Publication Year: 2012 , Page(s): xi
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  • Foreword from the CPSNA 2012 Co-Chairs

    Publication Year: 2012 , Page(s): xii
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  • RTCSA 2012 Organization

    Publication Year: 2012 , Page(s): xiii - xv
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  • CPSNA 2012 Workshop Organization

    Publication Year: 2012 , Page(s): xvi
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  • Software Controlled Memories for Scalable Many-Core Architectures

    Publication Year: 2012 , Page(s): 1 - 10
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3097 KB) |  | HTML iconHTML  

    Technology scaling along with the ever evolving demand for media-rich software stacks have motivated the need for many-core platforms. With the increase in compute power and its inherent demand for high memory bandwidth comes the need for vast amounts of on-chip memory space. Thus, designers must carefully provision the memory real-estate to meet their application's needs. It has been shown in the embedded systems domain that both software controlled memories (e.g., scratchpad memories) and hardware-controlled memories (e.g., caches) have their pros and cons, some application domains such as multimedia fit very well in the software-controlled memory model, while other domains such as databases work well with caches. As a result, efficient memory management is extremely critical as it has a great impact on the system's power consumption and throughput. Traditional memory hierarchies primarily consist of SRAM-based on-chip caches, however, with the emergence of non-volatile memories (NVMs) and mixed-criticality systems, on-chip memories will be heterogeneous, not only in type (cache vs. scratchpad) but also in technology (e.g., SRAM vs. NVM). This paper surveys the state of the art in memory subsystems for many-core platforms, and presents strategies for efficiently managing software-controlled memories in the many-core domain, while addressing the various challenges designers face in deploying such memory subsystems (e.g., sharing the memory resources, accounting for variations in the subsystem, etc.). View full abstract»

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  • Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling

    Publication Year: 2012 , Page(s): 11 - 20
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB) |  | HTML iconHTML  

    With the rapid progress in semiconductor technology and the shrinking of device geometries, the resulting processors are increasingly becoming prone to effects like aging and soft errors. As a processor ages, its electrical characteristics degrade, i.e., the switching times of its transistors increase. Hence, the processor cannot continue error-free operation at the same clock frequency and/or voltage for which it was originally designed. In order to mitigate such effects, recent research proposes to equip processors with special circuitry that automatically adapts its clock frequency in response to changes in its circuit-level timing properties (arising from changes in its electrical characteristics). From the point of view of tasks running on these processors, such autonomic frequency scaling(AFS) processors become slower as they gradually age. This leads to additional execution delay for tasks, which needs to be analyzed carefully, particularly in the context of hard real time or safety-critical systems. Hence, for real-time systems based on AFS processors, the associated schedulability analysis should be aging-aware which is a relatively unexplored topic so far. In this paper we propose a schedulability analysis framework that accounts such aging-induced degradation and changes in timing properties of the processor, when designing hard real-time systems. In particular, we address the schedulability and task mapping problem by taking a lifetime constraint of the system into account. In other words, the system should be designed to be fully operational (i.e., meet all deadlines) till a given minimum period of time (i.e., its lifetime). The proposed framework is based on an aging model of the processor which we discuss in detail. In addition to studying the effects of aging on the schedulability of real-time tasks, we also discuss its impact on task mapping and resource dimensioning. View full abstract»

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  • An Optimal Real-Time Voltage and Frequency Scaling for Uniform Multiprocessors

    Publication Year: 2012 , Page(s): 21 - 30
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    Power consumption is an increasing concern in real-time systems that operate on battery power or require heat dissipation to keep the system at its operating temperature. Today, most processors allow software to change their frequency and voltage of operation to reduce their power consumption. Frequency scaling in real-time systems must be done in a way that ensures that the tasks' deadlines are met. In this paper we present the Growing Minimum Frequency (GMF) algorithm for voltage and frequency scaling in uniform multiprocessors for real-time systems. This algorithm runs in polynomial time and computes the optimal voltage and frequency assignment, achieving better power efficiency than previous algorithms. We present the optimality proof and evaluate the practical improvement over previous algorithms with simulated task sets. Our evaluation shows up to to 30% power efficiency improvement over previous algorithms. View full abstract»

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  • Real-Time Scheduling of Energy Harvesting Embedded Systems with Timed Automata

    Publication Year: 2012 , Page(s): 31 - 40
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    In this paper, we propose feasibility and schedulability tests for a real-time scheduling problem under energy constraints. We first introduce the problem and show how to model it using timed automata. We then propose a feasibility test based on CTL model checking and schedulability tests for EDF and Preemptive Fixed Priority algorithms (PFP). Our approach also permits to generate a feasible schedule if one exists or otherwise to find how to correct battery characteristics to make the problem feasible. It is finally possible to generate schedules that optimize some criteria, such as the number of context switches between the battery recharging and discharging modes, the minimal and the maximal energy levels reached during the execution, or the number of preemptions. The approach is illustrated by some experiments using the model checking tool UPAAL [1]. View full abstract»

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  • Thermal-Constrained Energy-Aware Partitioning for Heterogeneous Multi-core Multiprocessor Real-Time Systems

    Publication Year: 2012 , Page(s): 41 - 50
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    Next-generation multi-core multiprocessor real-time systems consume less energy at the cost of increased power density. This increase in power-density results in high heat density and may affect the reliability and performance of real-time systems. Thus, incorporating maximum temperature constraints in scheduling of real-time task sets is an important challenge. This paper investigates thermal-constrained energy-aware partitioning of periodic real-time tasks in heterogeneous multi-core multiprocessor systems. We adopt a power model which considers the impact of temperature and voltage on a processor's static power consumption. Two types of thermal models are used to respectively capture negligible and non-negligible amount of heat transfer among cores. We develop a novel genetic-algorithm based approach to solve the heterogeneous multi-core multiprocessor partitioning problem. Extensive simulations were performed to validate the effectiveness of the approach. Experimental results show that integrating a worst-fit based partitioning heuristic with the genetic algorithm can significantly reduce the total energy consumption of a heterogeneous multi-core multiprocessor real-time system. View full abstract»

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  • Distributed IPC Using Virtual Device Driver in Monolithic Kernel

    Publication Year: 2012 , Page(s): 51 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    The applications of distributed computing are ubiquitous ranging from client/server based Internet systems to the cluster or grid and cloud computing systems. The distributed applications require efficient and transparent distributed interprocess communication (IPC) mechanism as a service from the operating systems supporting those applications. This paper describes the designed architecture and implementation of kernel-level distributed IPC mechanism using device driver framework offering transparency and high performance. The implementation is made in Linux monolithic kernel and the performance is measured by conducting the experiments in real-life execution environments. The experimental data illustrate that the distributed IPC in Ethernet network takes 629Ýs for small messages (25Bytes) and 2929Ýs for relatively large messages (5KB). The experiments in wireless network achieve 34528Ýs and 42511Ýs for the small and large messages, respectively. On the average, the designed architecture achieves distributed IPC time as 0.899Ýs/Byte in Ethernet and 92.628Ýs/Byte in wireless network environments. The proposed architecture and implementation offer 12.73% ~ 75.84% enhanced performance as compared to other distributed IPC models depending upon data length. View full abstract»

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  • Timing Analysis of Small Aircraft Transportation System (SATS)

    Publication Year: 2012 , Page(s): 58 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB) |  | HTML iconHTML  

    The Small Aircraft Transportation System (SATS) protocol, developed at NASA, aims to increase air transportation access for smaller communities and improve the transportation of people, services, and goods by a more effective use of over 5,000 small public airports in the United States. By using model checking and I/O automata, a number of different groups have verified many of the operational properties of SATS. However, none of the published work considers the timing constraints of the protocol, delegating instead to the pilot the responsibility for providing appropriate delays and separation assurance among events. In this paper, we formally specify the delays and the deadlines for the landing component of the protocol for simultaneous approaches of several small aircraft. This helps increase pilot safety for landing in these small airports. Linear Real-Time Logic (LRTL), a subclass of Real-Time Logic, and its associated toolset are utilized to analyze and formally verify the timing constraints of the landing component of SATS. In addition, an algorithm for debugging a subset of LRTL models is proposed. View full abstract»

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  • MinMax: A Sampling Interval Control Algorithm for Process Control Systems

    Publication Year: 2012 , Page(s): 68 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (322 KB) |  | HTML iconHTML  

    The traditional sampling method in process control systems is based on a periodic task model. This is because controllers are executed in a strictly periodic manner. Sensors sample the process data and send it periodically to the appropriate controllers through a communication system such as the field bus. Since the field bus is shared by multiple sensors, there is some delay (control loop latency)between the sampling and control actions. In order to minimize the control loop latency, a higher than necessary sampling frequency is typically adopted, which results in unnecessary waste of energy. In this paper, we propose Min Max: a sampling interval control algorithm for tackling this problem. In Min Max, sampling tasks are not periodic but have both maximum and minimum distance constraints. This sampling model has advantages that are especially important in the domain of wireless control for industrial automation. We shall then discuss the jitter property of sampling schemes under this model and propose algorithms for controlling the sampling intervals of sensors in terms of the Min Max problem (UMin Max) which we shall introduce. Though this problem is NP-hard in general, even for special case of unit-time tasks, we show how to reduce Min Max to well-studied scheduling models such as Liu and Layland-type periodic models and pinwheel models, at the expense of some loss of schedulability. These reductions allow us to derive efficient schedulability tests that can be used to solve the sampling interval control problem in practice. Simulations are used to compare the performance of different UMin Max schedulers in two key figures of merit: the acceptance ratio and the jitter ratio. Simulation of a process control system model also shows that UMin Max can reduce about 40% of the traffic load on the communication system which is especially important for energy-aware wireless process control applications. View full abstract»

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  • CSS: Conditional State-Based Scheduling for Networked Control Systems

    Publication Year: 2012 , Page(s): 78 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (345 KB) |  | HTML iconHTML  

    Modern industrial networked control systems(NCSs) tend to be complicated and have dynamic workload by holding a variety of applications via a shared network. The static network scheduling algorithms fit most NCSs due to their deterministic characteristics and timing guarantees, but they cannot handle dynamic workloads for lack of making on the-fly decisions. The conditional state-based scheduling adds the dynamism in the static scheduling algorithms by automata or more explicitly state chart like formalisms with conditional transitions. In this paper, we propose CSS scheme that applies the conditional state-based scheduling to dynamically schedule different applications in the industrial NCSs. CSS aims at the time-triggered network in the NCSs and uses time division multiple access (TDMA) method to let the applications access the network. To enhance the scalability of the NCSs, we design CSS as a decentralized scheme where each application in NCSs has a local scheduler to make its schedule decisions. Appropriate algorithms are applied to ensure the scheduling decisions made by the local schedulers are consistent and the desired system performance can be achieved. Simulation results demonstrate the effectiveness of the proposed scheme compared to the static TDMA used in real-time networks. View full abstract»

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  • The Split-Phase Synchronisation Technique: Reducing the Pessimism in the WCET Analysis of Parallelised Hard Real-Time Programs

    Publication Year: 2012 , Page(s): 88 - 97
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    In this paper we present the split-phase synchronisation technique to reduce the pessimism in the WCET analysis of parallelised hard real-time (HRT) programs on embedded multi-core processors. We implemented the split-phase synchronisation technique in the memory controller of the HRT capable MERASA multi-core processor. The split-phase synchronisation technique allows reordering memory requests and splitting of atomic RMW operations, while preserving atomicity, consistency and timing predictability. We determine the improvement of worst-case guarantees, that is the estimated upper bounds, for two parallelised HRT programs. We achieve a WCET improvement of up to 1.26 with the split-phase synchronisation technique, and an overall WCET improvement of up to 2.9 for parallel HRT programs with different software synchronisations. View full abstract»

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  • Energy Minimizing for Parallel Real-Time Tasks Based on Level-Packing

    Publication Year: 2012 , Page(s): 98 - 103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    While much work has addressed energy minimizing problem of real-time sequential tasks, little has been done for the parallel real-time task case. In this paper, based on level-packing, we study energy minimization problem for parallel task systems with discrete operation modes and under timing constraints. For tasks with fixed (variable) parallel degrees, we first formulate the problem as a 0-1 Integer Linear Program (0-1 ILP), and then propose a polynomial-time complexity two-step (three-step) heuristic to determine task schedule and frequency assignment (and the task parallel degree). Our simulation result shows that the heuristics consume nearly the same energy as do 0-1 ILPs. View full abstract»

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  • MCFlow: A Real-Time Multi-core Aware Middleware for Dependent Task Graphs

    Publication Year: 2012 , Page(s): 104 - 113
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB) |  | HTML iconHTML  

    Driven by the evolution of modern computer architectures from uni-processor to multi-core platforms, there is an increasing need to provide light-weight, efficient, and predictable support for fine-grained parallel and distributed execution of soft real-time tasks with end-to-end timing constraints, modeled as directed a cyclic graphs whose edges capture dependences among their subtasks. At the same time, there is a need to support state of the art programming models such as distributed components, whose ability to encapsulate functionality and allow context-specific optimizations is essential to manage the increasing complexity of modern distributed real-time and embedded systems and systems-of-systems. Real-time distributed middleware such as RT-CORBA has not kept pace with these developments, and a new generation of middleware is needed that can map these dependent subtask graphs onto distributed hosts with multi-core architectures, efficiently and within a simple, lightweight, and intuitive component programming model. To overcome these limitations, we have designed and implemented MC Flow, a novel distributed real-time component middleware for dependent subtask graphs running on multi-core platforms. MC Flow provides three new contributions to the state of the art in real-time component middleware: (1) a very lightweight component model that facilitates system integration and deployment through automatic code generation at compile time from a deployment plan specification, (2) transparent optimization of inter-component communication, and (3) the use of interface polymorphism to separate functional correctness from data copying and other performance constraints so that they can be configured and enforced independently but in a type-safe manner. Empirical evaluations of our approach in comparison to the widely used TAO real-time middleware show that MC Flow performs comparably to TAO when only one core is used and outperforms TAO when multiple cores are involve- . View full abstract»

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  • Supporting Soft Real-Time Parallel Applications on Multicore Processors

    Publication Year: 2012 , Page(s): 114 - 123
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    The prevalence of multicore processors has resulted in the wider applicability of parallel programming models such as Open MP and MapReduce. A common goal of running parallel applications implemented under such models is to guarantee bounded response times while maximizing system utilization. Unfortunately, little previous work has been done that can provide such performance guarantees. In this paper, this problem is addressed by applying soft real-time scheduling analysis techniques. Analysis and conditions are presented for guaranteeing bounded response times for parallel applications under global EDF multiprocessor scheduling. View full abstract»

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  • The Hyperbolic Schedulability Bound for Multiprocessor RM Scheduling

    Publication Year: 2012 , Page(s): 124 - 133
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    To verify the feasibility of real-time task sets on homogeneous multiprocessor systems, Lopez et al. derived the utilization bound based on Best Fit Decreasing allocation algorithm and Rate-Monotonic scheduling, which coincides with the maximum achievable multiprocessor utilization bound, using Liu & Lyland bound as the uniprocessor schedulability condition. In this paper, a novel feasibility test for the same target problem is developed based on the hyperbolic bound due to Bini et al., instead of the Liu & Layland bound. Analytical and experimental results show that the proposed utilization bound performs better than the existing bound under quite a lot of parameter settings, and combining these two bounds together can significantly increase the number of schedulable task sets with little extra overhead. View full abstract»

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  • Reducing Preemptions and Migrations in EKG

    Publication Year: 2012 , Page(s): 134 - 143
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (822 KB) |  | HTML iconHTML  

    EKG is a multiprocessor scheduling algorithm which is optimal for the scheduling of real-time periodic tasks with implicit deadlines. It consists in a semi-partitioned algorithm which adheres to the deadline partitioning fair (DP-Fair) theory. It was shown in recent studies that the division of the time in slices bounded by two successive deadlines and the systematic execution of migratory tasks in each time slice inherent in DP-Fair algorithms, significantly reduce the practicality of EKG. Nevertheless, its semi-partitioned approach allows to bound the number of migrating tasks and increases the locality of the tasks in memories, thereby lowering the time overheads imposed by task preemptions and migrations. Hence, we propose two techniques with the aim of reducing the amount of preemptions and migrations incurred by the system when scheduled with EKG, while maintaining the advantages of its semi-partitioned approach. The first improvement consists in a swapping algorithm which exchanges execution time between tasks and time slices. The second one aims at decreasing the number of time slices needed to ensure that all job deadlines are respected. Both have a strong impact on the number of preemptions and migrations while keeping the optimality of EKG. View full abstract»

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  • Partitioned Scheduling of Implicit-deadline Sporadic Task Systems under Multiple Resource Constraints

    Publication Year: 2012 , Page(s): 144 - 153
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    On many multiprocessor platforms each individual processor may have limited amounts of several different kinds of resources such as computing capacity, local memory, and network bandwidth. In order to partition tasks effectively upon such platforms the partitioning algorithm should be cognizant of all the resource constraints. We present and evaluate an algorithm for partitioning a collection of implicit-deadline sporadic tasks upon a multiprocessor platform in a manner that is cognizant of multiple such resource constraints. View full abstract»

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