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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems

7-9 May 2012

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  • [Front cover]

    Publication Year: 2012, Page(s): C1
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  • [Title page i]

    Publication Year: 2012, Page(s): i
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  • [Title page iii]

    Publication Year: 2012, Page(s): iii
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  • Copyright (c) 2012 by The Institute of Electrical and Electronics Engineers, Inc.

    Publication Year: 2012, Page(s): iv
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  • Table of contents

    Publication Year: 2012, Page(s):v - vii
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  • Message from the Chairs - ASYNC 2012

    Publication Year: 2012, Page(s):viii - ix
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  • Symposium Committee

    Publication Year: 2012, Page(s): x
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  • Technical Program Committee

    Publication Year: 2012, Page(s): xi
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  • Additional reviewers - ASYNC 2012

    Publication Year: 2012, Page(s): xii
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  • Steering Committee

    Publication Year: 2012, Page(s): xiii
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  • Keynotes

    Publication Year: 2012, Page(s):xiv - xvi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (134 KB)

    Summary form only given. Provides an abstract for each of the two keynote presentations and a brief professional biography of each presenter. View full abstract»

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  • Statistical Analysis and Optimization of Asynchronous Digital Circuits

    Publication Year: 2012, Page(s):1 - 8
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    This paper presents a statistical framework to analyze the performance of CMOS digital circuit in the presence of process variations considering a variety of timing methodologies. We first develop an analytical model that accurately predicts the circuit variability across a wide range of supply voltage and logic depth in 65nm CMOS technology. We then present a statistical analysis model to estimat... View full abstract»

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  • Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior

    Publication Year: 2012, Page(s):9 - 16
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (545 KB) | HTML iconHTML

    Asynchronous circuits with conditional behavior often have distinct modes of operation each of which can be modeled as a marked graph with its own performance target. This paper derives performance bounds for such conditional circuits based on the cycle times of successively larger collections of these underlying modes. Our bounds prove the somewhat intuitive result that treating a conditional cir... View full abstract»

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  • Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation

    Publication Year: 2012, Page(s):17 - 24
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB) | HTML iconHTML

    Modern hardware systems are required to be robust, resilient and long-life, thus they have to be adaptive to changing requirements and operating conditions. This covers not only the data processing functions but also control and timing/power operation. For example, such systems will be increasingly powered by ambient sources (energy harvesting) and will experience a wide range of modes, including ... View full abstract»

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  • A Digital Neurosynaptic Core Using Event-Driven QDI Circuits

    Publication Year: 2012, Page(s):25 - 32
    Cited by:  Papers (16)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (870 KB) | HTML iconHTML

    We design and implement a key building block of a scalable neuromorphic architecture capable of running spiking neural networks in compact and low-power hardware. Our innovation is a configurable neurosynaptic core that combines 256 integrate-and-fire neurons, 1024 input axons, and 1024×256 synapses in 4.2mm2 of silicon using a 45nm SOI process. We are able to achieve ultra-low e... View full abstract»

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  • A Low Power Asynchronous GPS Baseband Processor

    Publication Year: 2012, Page(s):33 - 40
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    We present the design and implementation of an asynchronous Global Positioning System (GPS) base band processor architecture designed with a combination of Quasi-Delay-Insensitive (QDI) and bundled-data techniques, with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly. Transistor-level simulations s... View full abstract»

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  • High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

    Publication Year: 2012, Page(s):41 - 48
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB) | HTML iconHTML

    This paper introduces a self-timed overlapped search mechanism for high-throughput content-addressable memories (CAMs) with low search energy. Most mismatches can be found by searching the first few bits in a search word. Consequently, if a word circuit is divided into two sections that are sequentially searched, most match lines in the second section are unused. As searching the first section is ... View full abstract»

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  • An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery

    Publication Year: 2012, Page(s):49 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    Delay Locked Loops (DLLs) have become a standard structure in IC design, providing programmable, calibrated on-chip delays. They can be used, for example, to deskew clocks by matching delay paths. One application is in data recovery from DDR SDRAMs whose data strobe edges need retarding to provide adequate setup times for latching read data. The DLL described here was developed as a solution to th... View full abstract»

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  • A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous Systems

    Publication Year: 2012, Page(s):57 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB) | HTML iconHTML

    This paper proposes a novel hierarchical approach for scheduling shared resources in asynchronous pipelined systems. While there have been recent approaches to asynchronous resource scheduling, the problem is especially difficult for multi-token systems, i.e., systems where computation on multiple problem instances is overlapped and pipelined, so resources are shared amongst operations across diff... View full abstract»

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  • Uncle - An RTL Approach to Asynchronous Design

    Publication Year: 2012, Page(s):65 - 72
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (361 KB) | HTML iconHTML

    Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, data path elements, and finite state machines for controlling data path sequencing. A commercial synthesis tool is used to produce a gate-level net list of primitive ... View full abstract»

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  • A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits

    Publication Year: 2012, Page(s):73 - 80
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    In this paper, we present a performance-oriented implementation flow for WCHB QDI asynchronous circuits aiming to be fully compatible with conventional EDA tools for synchronous designs. Starting from a simple standard-cell library for asynchronous logic, this flow builds pseudo-synchronous models of the cells. With these models, a simple set of pseudo-synchronous timing constraints can be given t... View full abstract»

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  • Ultra Low Power Booth Multiplier Using Asynchronous Logic

    Publication Year: 2012, Page(s):81 - 88
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1346 KB) | HTML iconHTML

    Asynchronous logic shows promising applicability in ASIC design due to its potentially low power and high robustness properties. For deep submicron technologies the static power is becoming very significant and many applications require that this power component to be reduced. A new logic called Positive Feedback Charge Sharing Logic (PFCSL) is proposed, which reduces both dynamic and especially s... View full abstract»

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  • An Asynchronous Floating-Point Multiplier

    Publication Year: 2012, Page(s):89 - 96
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (887 KB) | HTML iconHTML

    We present the details of our energy-efficient asynchronous floating-point multiplier (FPM). We discuss design trade-offs of various multiplier implementations. A higher radix array multiplier design with operand-dependent carry-propagation adder and low handshake overhead pipeline design is presented, which yields significant energy savings while preserving the average throughput. Our FPM also in... View full abstract»

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  • An Asynchronous Divider Implementation

    Publication Year: 2012, Page(s):97 - 104
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    We present an asynchronous implementation of a novel division algorithm previously patented. Our implementation exploits the average-case behavior of the algorithm and uses the versatility of GasP circuits to implement the data-dependent latencies in the algorithm. On average, the delay per quotient bit for our implementation is 6.3 FO4 gate delays compared to 9.5 FO4 gate delays for a similar SRT... View full abstract»

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  • Tiempo Asynchronous Circuits System Verilog Modeling Language

    Publication Year: 2012, Page(s):105 - 112
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (219 KB) | HTML iconHTML

    This paper describes the System Verilog modeling language developed by Tiempo to design asynchronous circuits. The language enables designers to model, verify and debug asynchronous circuits using standard simulators, viewers and debuggers. The paper first highlights how the concept of communication channel is supported and how System Verilog is used to declare channels and ports, reading and writ... View full abstract»

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