Date 12-14 June 2012
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Displaying Results 1 - 25 of 97
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[Copyright notice]
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PDF (78 KB)
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Foreword
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PDF (79 KB)
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Committees
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PDF (74 KB)
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Program
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PDF (188 KB)
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Peering through the technology scaling fog
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PDF (463 KB)
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10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V
th tunability through thin BOX
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PDF (395 KB)
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Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width
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PDF (1034 KB)
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FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface
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PDF (673 KB)
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A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory
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PDF (476 KB)
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A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices
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PDF (193 KB)
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Implementing cubic-phase HfO
2 with κ-value ∼ 30 in low-VT replacement gate pMOS devices for improved EOT-Scaling and reliability
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PDF (553 KB)
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A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
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PDF (452 KB)
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Dramatic improvement of high-k gate dielectric reliability by using mono-layer graphene gate electrode
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PDF (373 KB)
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Process control & integration options of RMG technology for aggressively scaled devices
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PDF (783 KB)
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Varistor-type bidirectional switch (J
MAX >107A/cm2, selectivity∼104) for 3D bipolar resistive memory arrays
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PDF (1152 KB)
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Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield
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PDF (3503 KB)
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