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Silicon Nanoelectronics Workshop (SNW), 2012 IEEE

Date 10-11 June 2012

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  • 2012 IEEE Silicon Nanoelectronics Workshop [cover]

    Publication Year: 2012 , Page(s): i
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  • 2012 IEEE Silicon Nanoelectronics Workshop [Copyright notice]

    Publication Year: 2012 , Page(s): ii
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  • Welcome message

    Publication Year: 2012 , Page(s): iii
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  • Committee members for the 2012 IEEE silicon nanoelectronics workshop

    Publication Year: 2012 , Page(s): iv
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  • 2012 IEEE Silicon Nanoelectronics Workshop [Technical program]

    Publication Year: 2012 , Page(s): v - xii
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  • Innovative thermal energy harvesting for zero power electronics

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1451 KB) |  | HTML iconHTML  

    Thermal gradients, commonly present in our environment (fluid lines, warm fronts, electronics) are sources of energy rarely used today. This paper aims to present innovative approaches of thin and/or flexible thermal energy harvesters for smart and autonomous sensor network applications. The harvester system will be based on the collaborative work of interrelated energy nodes/units, which will be either piezo-thermofluidic converters (use of rapid thermal cycles of a working fluid) or piezo-thermomechanic converters (use of the mechanical energy developed by rapid snapping of micro-switches). The two kinds of energy nodes convert a heat flux into storable electrical energy through a piezoelectric transducer. Miniaturization of the energy nodes will lead to increased thermal transfer rates and consequently increased harvested power. To effectively use thermal energy sources in varying environments, the nodes will be adaptive versus different thermal gradients (in a predefined temperature range) and will possibly influence each other. The concept is unique in the sense that it is based on a matrix structure of micro or mini energy nodes which will work together in a collective approach to optimize the harvested energy, and which do not require the use of radiators as classical Seebeck approach, thanks to the controlled thermal resistance. This opens the door to new properties and features of the object, with better performances. It could therefore be declined on flexible substrates, allowing conformability around the sources of potential heat for low power applications. View full abstract»

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  • New type steep-S device using the bipolar action

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (214 KB) |  | HTML iconHTML  

    We have proposed an alternative approach for developing a steep subthreshold swing FET that is less than the theoretical diffusion-based limit of 60 mV/decade at room temperature. Instead of using a simple IGFET, we formed a complex device in a “single device” and worked it as a sub-circuit, which resulted in a steep subthreshold swing. We formed a tunnel junction in a drain diffusion layer of the MOSFET so that we could stuff a tunnel-injection bipolar, a resistor, and a MOSFET inside a single “scaled MOSFET”. We used device simulation to clarify the concept of “device complex”. Results showed a steep subthreshold swing even if the supply voltage was low (~0.2 V). View full abstract»

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  • Experimental demonstration of temperature stability of Si-tunnel FET over Si-MOSFET

    Publication Year: 2012 , Page(s): 1 - 2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (345 KB) |  | HTML iconHTML  

    Temperature dependences of tunnel field-effect transistor (TFET) and MOSFET were experimentally compared on the same SOI wafer. Validity of the TFET result was corroborated by simulation. It is demonstrated that VTH shift and off-current increment of Si-TFET with temperature were smaller in comparison with Si-MOSFET. Temperature stability of TFET is promising for ultra-low power VLSI. View full abstract»

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  • Scale laws for enhanced power for MEMS based heat energy harvesting

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (277 KB) |  | HTML iconHTML  

    An innovation approach to thermal energy harvesting is presented. It consists of a two step conversion of heat into electricity. The new technique can be used for powering ultra-low power electronics and autonomous systems. One of the keys to improve the generated power density is downscaling of individual devices. Laws modeling downscaling have been established in this paper and show that the miniaturization of the devices by a factor k increases the generated power density by the same factor, due to the increased speed of heat transfer. The scaling laws predict increasing power gain when miniaturizing the devices with use of e.g. VLSI technologies. This can help in providing a strong alternative to Seebeck devices. View full abstract»

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  • Energy-efficiency and thermal management in nanoscale devices

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    Power consumption and thermal management are significant challenges in electronics, from mobile devices to data centers. A fundamental examination of such aspects could lead to orders of magnitude improvements in energy efficiency. We present recent highlights from our work examining dissipation in nanoscale devices, at contacts, interfaces, and in novel materials. Advances include the use of high-thermal conductivity materials (graphene), low-power data storage (based on phase change rather than charge), and thermoelectric effects for highly localized cooling. Results suggest much room to improve power dissipation in nanoscale electronics, towards fundamental limits, through the co-design of geometry and materials. View full abstract»

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  • Comparative study of tri-gate- and double-gate-type poly-Si fin-channel split-gate flash memories

    Publication Year: 2012 , Page(s): 1 - 2
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    The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n+-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller Vt variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. Moreover, it was also confirmed that over-erase is effectively suppressed by split-gate structure. View full abstract»

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  • Variation-aware study of BJT-based capacitorless DRAM cell scaling limit

    Publication Year: 2012 , Page(s): 1 - 2
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB) |  | HTML iconHTML  

    The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application. View full abstract»

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  • Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

    Publication Year: 2012 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG). View full abstract»

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  • A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB) |  | HTML iconHTML  

    A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The process is simple and mask free. For the 3-nm-thick channel devices, the S.S. of 88 mV/dec and Ion/Ioff ratio of more than 108 can be achieved. Extreme low applied voltage for band-to-band-tunneling-induced hot electron injection tunneling (BBHE) operation and excellent retention are proposed. View full abstract»

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  • Graphene for More Moore and More Than Moore applications

    Publication Year: 2012 , Page(s): 1 - 3
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (873 KB) |  | HTML iconHTML  

    Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment and high contact resistance. In addition, graphene has no energy band gap and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour. This has steered interest away from logic to analog radio frequency (RF) applications. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology. GFETs slightly lag behind in maximum cut-off frequency FT,max up to a carrier mobility of 3000 cm2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves. View full abstract»

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  • High performance Ω-gate Ge FinFET featuring low temperature Si2H6 passivation and implantless Schottky-barrier NiGe metallic Source/Drain

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (637 KB) |  | HTML iconHTML  

    We report the first Ω-gate Germanium (Ge) p-channel FinFET with low-temperature Si2H6 passivation and implantless Schottky-barrier nickel germanide (NiGe) metallic Source/Drain, formed on high-quality GeOI substrates using sub-400 °C process modules. As compared with reported multi-gate (MuG) Ge devices in which the Ge channels were formed by top-down approaches, the Ge FinFETs in this work have a record high on-state current ION of ~494 μA/μm at VGS - VTH = -1 V and VDS = -1 V. A high ION/IOFF ratio of more than 3×104 and a high peak saturation transconductance GMSatMax of ~540 μS/μm were achieved. View full abstract»

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  • High-performance pMOSFETs with high-k gate dielectric and dislocation-free epitaxial Si/Ge super-lattice channel

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB) |  | HTML iconHTML  

    The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process. View full abstract»

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  • Counter dipole layer formation in SiO2/high-k/SiO2/Si gate stacks

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    This paper presents experimental results of the counter dipole formation in SiO2/high-k (Al2O3 and Y2O3)/SiO2/Si gate stacks for the first time. The results definitely support the high-k/SiO2 interface dipole layer formation in metal/high-k gate CMOS. View full abstract»

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  • Simultaneous carrier transport enhancement and variability reduction in Si MOSFETs by insertion of partial monolayers of oxygen

    Publication Year: 2012 , Page(s): 1 - 2
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer. View full abstract»

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  • Transport in graphene on boron nitride

    Publication Year: 2012 , Page(s): 1 - 2
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    Graphene has become of great interest in recent years for its unique band structure and prospective importance in both microwave and logic devices. Recently, the use of a boron nitride layer between the graphene and the silicon dioxide substrate has shown enhanced mobilities due to displacing the disorder charge, typical on the oxide, further from the graphene material. On the other hand, like the oxide, boron nitride has polar optical modes which can interact with the carriers in graphene to lower their mobility. We have used an ensemble Monte Carlo technique to study the transport in graphene on a boron nitride layer. Scattering by the intrinsic phonons of graphene, as well as by the flexural modes of the rippled layer, and the remote polar mode of boron nitride has been included. The flexural modes are described by the model of Castro et al. While the EMC uses the simple Dirac band structure, coupling constants for the intrinsic phonon modes are taken by fitting to scattering rates determined from first-principles calculations. We find that, at low temperatures, the mobility is dominated primarily by the intrinsic graphene phonons and the flexural modes. This arises as the interfacial polar mode of boron nitride lies at an energy of 200 meV, which is largely too high to interact well with the majority of the carriers in graphene. On the other hand, at room temperature, the mobility begins to be dominated by the remote polar mode of the boron nitride. Nevertheless, the prospects of reaching a high velocity, needed for device performance particularly at microwave frequencies, remains very good. View full abstract»

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  • Magnetic tunnel junction for magnetoresistive random access memory and beyond

    Publication Year: 2012 , Page(s): 1 - 2
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    I have reviewed current status of MTJ and how it can be used in memories and logic circuits, referring to some of our recent implementations. The ultimate scalability of MTJ technology will be determined by both materials involved and processing technology. It is difficult to foresee how far in dimension one can go at this point. But we should be able to learn from the materials science for hard disk media that can realize high Δ at dimensions less than 10nm and is continuing to develop a patterned one. View full abstract»

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  • Systolic architectures and applications for nanomagnet logic

    Publication Year: 2012 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (549 KB) |  | HTML iconHTML  

    Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented. View full abstract»

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  • Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs

    Publication Year: 2012 , Page(s): 1 - 2
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    Static noise margins (SNMs) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNMs as an optimized 6T-SRAM cell. SNMs for other recently-proposed NV-SRAM cells using STT-MTJs were also evaluated, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode. View full abstract»

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  • Recent progress of resistive switching random access memory (RRAM)

    Publication Year: 2012 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (943 KB) |  | HTML iconHTML  

    This paper gives an overview of recent works on metal oxide resistive switching memory (RRAM). We explored the stochastic nature of resistive switching in metal oxide RRAM and a 2-D analytical solver was established to explain the switching parameter variations in HfOx-based RRAM. As an example of application beyond digital memory/storage, AlOx-based RRAM was explored for neuromorphic computing. View full abstract»

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  • Bidirectional selection device characteristics of ultra-thin (<3nm) TiO2 layer for 3D vertically stackable ReRAM application

    Publication Year: 2012 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    We propose the feasibility of bidirectional selection device characteristics in ultrathin (<;3nm) TiO2 layer. We utilized the localized conducting path as virtual electrode to investigate device property at extremely scaled area. By using electrical method such as “forming” and “reset” processes in oxide, virtual electrode/sub-3nm-thick TiO2/virtual electrode structure was achieved. The measured current-voltage characteristics of fabricated device exhibited uniform bidirectional selection behavior with a high selectivity (~105) and showed the feasibility of high current density (>;106A/cm2). View full abstract»

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