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Electronic System Level Synthesis Conference (ESLsyn), 2012

Date 2-3 June 2012

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Displaying Results 1 - 14 of 14
  • [Front cover]

    Publication Year: 2012, Page(s): c1
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  • [Title page]

    Publication Year: 2012, Page(s): 2
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  • Table of contents

    Publication Year: 2012, Page(s): 3
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  • [Front matter]

    Publication Year: 2012, Page(s):4 - 9
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  • Session 1: High-level synthesis

    Publication Year: 2012, Page(s): 10
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  • Trimmed VLIW: Moving application specific processors towards high level synthesis

    Publication Year: 2012, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2992 KB) | HTML iconHTML

    We describe a synthesis methodology called Trimmed VLIW, which we argue lies between application specific processors and high level synthesis. Much like application specific processors, our methodology starts from a known instruction set architecture and customizes it to create the final implementation. However, our approach goes further as we not only add custom functional units and define the pa... View full abstract»

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  • A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs

    Publication Year: 2012, Page(s):17 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (235 KB) | HTML iconHTML

    High-level synthesis tools are gaining more and more acceptance in industrial design flows. While they increase productivity in implementing a single complex hardware module, synthesizing and optimizing many hardware components simultaneously is still an open problem. In particular, resource sharing is typically only performed for single components, thereby neglecting optimization possibilities ac... View full abstract»

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  • Session 2: Modelling

    Publication Year: 2012, Page(s): 23
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  • Synthesizing embedded software with safety wrappers through polyhedral analysis in a polychronous framework

    Publication Year: 2012, Page(s):24 - 29
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (379 KB) | HTML iconHTML

    Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Ref... View full abstract»

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  • Session 3: High-level synthesis

    Publication Year: 2012, Page(s): 30
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  • Transaction-accurate interface scheduling in high-level synthesis

    Publication Year: 2012, Page(s):31 - 36
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    The timing model for code presented to a high-level synthesis tool is an important factor in determining the level of abstraction which the HLS tool can support. There have been many attempts at defining a timing model. Here we survey some of the timing models that have been used, and present the transaction protocol model, used by Forte Design Systems' Cynthesizer, which has several advantages ov... View full abstract»

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  • Session 4: MPSoCs

    Publication Year: 2012, Page(s): 37
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  • Multi-layer configuration exploration of MPSoCs for streaming applications

    Publication Year: 2012, Page(s):38 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1353 KB) | HTML iconHTML

    While integration of configurable components, such as soft processors, in MPSoC design enables further system adaptation to application needs, supporting system level tools need to provide an environment for systematic and efficient configuration exploration. This paper presents a multi-layer configuration exploration framework for streaming applications on MPSoCs. We introduce a novel Configurati... View full abstract»

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  • Process variation-aware task replication for throughput optimization in configurable MPSoCS

    Publication Year: 2012, Page(s):44 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (271 KB) | HTML iconHTML

    Due to within-die and die-to-die variations, multiple cores in MPSoC have different delay distributions, and hence the problem of assigning tasks to the cores become challenging. This paper targets system level throughput optimization in streaming pipelined MPSoCs under process variation. First, to maximize system level throughput, we make extensive use of data parallelism of the streaming applica... View full abstract»

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