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Electronic System Level Synthesis Conference (ESLsyn), 2012

Date 2-3 June 2012

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Displaying Results 1 - 14 of 14
  • [Front cover]

    Page(s): c1
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  • [Title page]

    Page(s): 2
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  • Table of contents

    Page(s): 3
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  • [Front matter]

    Page(s): 4 - 9
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  • Session 1: High-level synthesis

    Page(s): 10
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  • Trimmed VLIW: Moving application specific processors towards high level synthesis

    Page(s): 11 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2992 KB) |  | HTML iconHTML  

    We describe a synthesis methodology called Trimmed VLIW, which we argue lies between application specific processors and high level synthesis. Much like application specific processors, our methodology starts from a known instruction set architecture and customizes it to create the final implementation. However, our approach goes further as we not only add custom functional units and define the parameters of the register file, but we also remove unneeded interconnect, which results in a data path that looks more similar to that created by high level synthesis tools. We show that there are substantial opportunities for eliminating unused resources, which results in an architecture that has significantly smaller area. We compare area, delay and performance results of a base architecture with trimmed one. Preliminary results show by only trimming wires we have an average of 25% area reduction while improving the performance around 5%. Furthermore, we evaluated our results with high-level synthesize tools C2V and AutoESL. View full abstract»

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  • A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs

    Page(s): 17 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    High-level synthesis tools are gaining more and more acceptance in industrial design flows. While they increase productivity in implementing a single complex hardware module, synthesizing and optimizing many hardware components simultaneously is still an open problem. In particular, resource sharing is typically only performed for single components, thereby neglecting optimization possibilities across concurrent modules. On the other hand, domain-specific models and specifications, which are generally seen as a key ingredient to raise the level of abstraction in future design flows, may enable such global optimizations. In this paper, we present a model-based approach for inter-process resource sharing which provides for efficient high-level synthesis of streaming applications modeled as a set of communicating processes. The applicability of the proposed approach is validated by a case study. View full abstract»

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  • Session 2: Modelling

    Page(s): 23
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  • Synthesizing embedded software with safety wrappers through polyhedral analysis in a polychronous framework

    Page(s): 24 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (379 KB) |  | HTML iconHTML  

    Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how integrating a Satisfiability Modulo Theory (SMT) solver to POLYCHRONY compiler can enhance its decision making capabilities. Further, we show, how a polyhedral analysis library integrated to the compiler, can compute safe operational boundaries, and filter unsafe input combinations to keep the system safe. We enhanced the POLYCHRONY compiler's ability to make more accurate decisions and to accept and characterize the safe input range for specifications where safety may be violated for a relatively small region of a large input space. The enhancement also allows the user to consider the severity of the violation with respect to entire space of inputs, and either reject a specification or synthesize a wrapped software with guaranteed safe operation. View full abstract»

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  • Session 3: High-level synthesis

    Page(s): 30
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  • Transaction-accurate interface scheduling in high-level synthesis

    Page(s): 31 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    The timing model for code presented to a high-level synthesis tool is an important factor in determining the level of abstraction which the HLS tool can support. There have been many attempts at defining a timing model. Here we survey some of the timing models that have been used, and present the transaction protocol model, used by Forte Design Systems' Cynthesizer, which has several advantages over previous timing models. View full abstract»

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  • Session 4: MPSoCs

    Page(s): 37
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  • Multi-layer configuration exploration of MPSoCs for streaming applications

    Page(s): 38 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1353 KB) |  | HTML iconHTML  

    While integration of configurable components, such as soft processors, in MPSoC design enables further system adaptation to application needs, supporting system level tools need to provide an environment for systematic and efficient configuration exploration. This paper presents a multi-layer configuration exploration framework for streaming applications on MPSoCs. We introduce a novel Configuration Exploration Tree (CET) for configuration selection per processor. Integrated in a system-level design environment, our CET enables efficient and fully automatic exploration of processor configurations in MPSoC. The proposed CET supports the fast evaluation of feasible configurations by simulation at highest levels of abstraction. In addition, assuming monotonous impact of configuration values on system throughput, we use an ordering among the nodes in the CET to minimize necessary simulations. Our exploration efficiently finds all feasible configurations for a given constraint. View full abstract»

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  • Process variation-aware task replication for throughput optimization in configurable MPSoCS

    Page(s): 44 - 49
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    Due to within-die and die-to-die variations, multiple cores in MPSoC have different delay distributions, and hence the problem of assigning tasks to the cores become challenging. This paper targets system level throughput optimization in streaming pipelined MPSoCs under process variation. First, to maximize system level throughput, we make extensive use of data parallelism of the streaming applications to map them to multiple cores available on a chip. In order to tackle the effect of process variation in clock frequency of these cores, and the resulting deterioration in system timing yield, we propose to deploy frequency scaling and configuration selection for each core. We incorporate timing yield constraint during task replication and load balancing for data parallel tasks. The novel contribution of this work is that we perform all these operations simultaneously, and show the benefits of our approach. We present an ILP solution for maximum throughput under process variation and the proposed solution determines the right degree of parallelism at target timing yield. Our proposed ILP formulation is very generic and can be used for task replication of single or multiple tasks, while simultaneously performing optimum load balancing. The results show that the MPSoC system design flows that do not consider one or more than one of the above mentioned design decisions simultaneously, suffer greatly from the design failures and fail to meet strict timing yield and bandwidth constraints. The throughput of such an MPSoC system is also worse than half of the throughput of our proposed system. View full abstract»

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