IEEE Design & Test

Issue 6 • Dec. 2017

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  • Front Cover

    Publication Year: 2017, Page(s): C1
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  • Cover 2

    Publication Year: 2017, Page(s): C2
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  • IEEE Design&Test publication information

    Publication Year: 2017, Page(s): 1
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  • Table of Contents

    Publication Year: 2017, Page(s):2 - 3
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  • Self-Aware On-Chip Systems

    Publication Year: 2017, Page(s):4 - 5
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  • Guest Editorial: Special Issue on Self-Aware Systems on Chip

    Publication Year: 2017, Page(s):6 - 7
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  • Self-Awareness in Systems on Chip— A Survey

    Publication Year: 2017, Page(s):8 - 26
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    Editor’s note: Self-awareness is a desirable feature of emerging computing systems. It helps systems to understand, manage, and report on their own system behavior. This paper presents an overview centered around the paradigm of self-awareness in computing systems. —Partha Pratim Pande, Washington State University View full abstract»

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  • Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

    Publication Year: 2017, Page(s):27 - 35
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1459 KB) | HTML iconHTML

    Motivated by the need to tolerate faults, this paper presents a complete fault management solution that includes fault detection and categorization, maintaining a map of faults, and modified scheduling and application algorithms for using healthy resources only. As the system maintains fairly sophisticated models of itself regarding faulty and healthy resources, it constitutes a good example of sp... View full abstract»

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  • KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications

    Publication Year: 2017, Page(s):36 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (831 KB) | HTML iconHTML

    Being aware of its own power consumption is essential for any system under power constraints, i.e. all systems with moderate or high complexity. This paper describes a tool that provides this power awareness for applications written in OpenCL and implemented on FPGAs. —Axel Jantsch, TU Wien View full abstract»

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  • A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors

    Publication Year: 2017, Page(s):46 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1885 KB) | HTML iconHTML

    As technology edges closer to fundamental limits, variations of process parameters, operational voltage, and temperature (PVT variations) have to be accounted for. This paper proposes to make higher levels aware of these variations and bring them under system control by using software controlled body biasing. PVT variations can thus be exploited to reduce power and energy consumption.— View full abstract»

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  • Self-Adaptive Timing Repair

    Publication Year: 2017, Page(s):54 - 62
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (667 KB) | HTML iconHTML

    This article describes a method to continuously monitor paths delays in an operational FPGA design and to improve slow paths by incremental partial reconfiguration. Since online delay measuring is more accurate than design time estimation, this approach allows to balance delays which can be used to improve performance or reduce power consumption. In addition, it counteracts aging effects and prolo... View full abstract»

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  • Trusted Analog/Mixed- Signal/RF ICs: A Survey and a Perspective

    Publication Year: 2017, Page(s):63 - 76
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1734 KB) | HTML iconHTML

    The trustworthiness of integrated circuits is now an essential technical and business challenge for the semiconductor industry. In the digital domain, there has been extensive activity in understanding and counteracting the threats of hardware Trojans, piracy and counterfeiting. However, this research area is largely nascent and understudied for analog/mixed-signal (AMS) and radio frequency (RF) c... View full abstract»

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  • Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis

    Publication Year: 2017, Page(s):77 - 83
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    The authors target the typical problem of a small number of test access ports. As a solution, they propose a set of interposers to obtain access to the tested nets. Jörg Henkel, Karlsruhe Institute of Technology View full abstract»

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  • Adaptive ECC for Tailored Protection of Nanoscale Memory

    Publication Year: 2017, Page(s):84 - 93
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1253 KB) | HTML iconHTML

    Following technology scaling, runtime failure has emerged as one of the major challenges in modern VLSI designs under the increased parametric variability and low supply voltage. This issue is especially severe in nanoscale memory due to its high density and large capacity. In this work the authors present a novel reconfigurable Error Correction Code (ECC) to improve the reliability of nanoscale m... View full abstract»

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  • Low-Power Sparse Hyperdimensional Encoder for Language Recognition

    Publication Year: 2017, Page(s):94 - 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (551 KB) | HTML iconHTML

    Online learning for data analysis, categorization and anomaly detection has become a key technique in a range of adaptive embedded applications. In this article the authors propose a very low power encoder design using a sparse, hyperdimensional representation of letters and words in natural language and they show that this representation and their design can be used with high energy efficiency fo... View full abstract»

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  • Internet of Things—The Quest for Trust

    Publication Year: 2017, Page(s):102 - 108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (101 KB) | HTML iconHTML

    Many believe that we will be surrounded by billions of connected devices that monitor physical, biological, chemical, or social processes. Society will increasingly depend on the Internet of Things. Trustworthy behavior is key for societal acceptance. In this article, we will only have a look at some of the underlying mechanisms, analyze them, and provide some corresponding design principles. In p... View full abstract»

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  • Nano-Tera.ch: Information Technology for Health, Environment, and Energy

    Publication Year: 2017, Page(s):109 - 118
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    Bettering human health care and creating a sustainable environment through monitoring and smart energy usage are primary goals of advanced societies. To this purpose, the Swiss Government, through the State Secretariat for Education, Research, and Innovation has been funding the Nano-Tera.ch program for about nine years with an overall budget of approximately 250 MUSD, half in cash, and half in ma... View full abstract»

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  • Recap of the European Test Symposium 2017 (ETS’17)

    Publication Year: 2017, Page(s):119 - 120
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  • Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED)

    Publication Year: 2017, Page(s):121 - 122
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  • CEDA Currents

    Publication Year: 2017, Page(s):123 - 124
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  • Test Technology TC Newsletter

    Publication Year: 2017, Page(s):125 - 126
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  • Call for Contributions Special Issue on Cyber Security for Embedded Controls in Cyber Physical Systems

    Publication Year: 2017, Page(s): 127
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  • Chips Thinking About Chips

    Publication Year: 2017, Page(s): 128
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  • Cover 3

    Publication Year: 2017, Page(s): C3
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  • Cover 4

    Publication Year: 2017, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)