By Topic

Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on

Date 18-20 April 2012

Filter Results

Displaying Results 1 - 25 of 95
  • IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Cover

    Publication Year: 2012 , Page(s): c1 - c4
    Save to Project icon | Request Permissions | PDF file iconPDF (2100 KB)  
    Freely Available from IEEE
  • Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) [Title page]

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (180 KB)  
    Freely Available from IEEE
  • 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) [Copyright notice]

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (132 KB)  
    Freely Available from IEEE
  • Foreword to the 15th IEEE DDECS Symposium

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (185 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Symposium committees

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (158 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2012 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | PDF file iconPDF (139 KB)  
    Freely Available from IEEE
  • On-line test of embedded systems: Which role for functional test?

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (69 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • TSV based 3D stacked ICs: Opportunities and challenges

    Publication Year: 2012 , Page(s): 2
    Save to Project icon | Request Permissions | PDF file iconPDF (88 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Vertical Slit Transistor based Integrated Circuits (VeSTICs)

    Publication Year: 2012 , Page(s): 3
    Save to Project icon | Request Permissions | PDF file iconPDF (88 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • 3D integration: Opportunities, design challenges and approaches

    Publication Year: 2012 , Page(s): 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (75 KB) |  | HTML iconHTML  

    Summary form only given. More than Moore technologies like 3D-integration enable the dense integration of different circuits. With the right partitioning of functional units in a die stack; the system performance can be increased and the power consumption reduced. Design of 3D-integrated systems requests the consideration of several electrical and multi-physical interactions in a stack, e.g. thermal management, power distribution and electromagnetic compatibility stronger than in 2D-SoC-design. Therefore new design flows and tools are under development. The tutorial outlines the current status of technologies and applications for 3D-integration and gives an overview on the design challenges. Approaches for 3D design-flow and algorithms will be presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Asynchronous circuit design: From basics to practical applications

    Publication Year: 2012 , Page(s): 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (75 KB) |  | HTML iconHTML  

    After motivating asynchronous techniques in general, the main advantages and disadvantages will be discussed. Several asynchronous timing models such as delay insensitive (DI) quasi delay insensitive (QDI) and speed independent (SI) will be presented and compared. Completion-detection methods used in asynchronous design are reviewed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automated synthesis and design-error repair of systems

    Publication Year: 2012 , Page(s): 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB) |  | HTML iconHTML  

    Due to the ever increasing complexity of digital systems, the need for formal verification methods has also been increasing steadily. Verification usually requires some form of specification. Having available a formal specification for a system, one can ask why designers have to bother fixing errors that have been detected. Or, going one step further, why not synthesize the entire system from the specification? We will have a look at two state-of-the-art automated and correct-by-construction synthesis methods that address these questions. First, we will consider property synthesis, which can be viewed as a game. Second, we show how to benefit from abstraction by uninterpreted functions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault management in an IEEE P1687 (IJTAG) environment

    Publication Year: 2012 , Page(s): 7
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (78 KB) |  | HTML iconHTML  

    Summary form only given. To meet the constant demand for performance, it is increasingly common with multi-processor system-on-chips (MPSoCs). As these integrated circuits (ICs) may contain billions of transistors squeezed on a few square centimeters, it is difficult to ensure that they are correct. Defects may escape manufacturing test or develop during operation and, further, ICs manufactured in later semiconductor technologies are increasingly sensitive to environmental disturbances. These defects may be permanent (hard) or transient (soft). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design methodology for fault tolerant ASICs

    Publication Year: 2012 , Page(s): 8 - 11
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (946 KB) |  | HTML iconHTML  

    The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a design methodology for a full fault tolerant ASIC that is immune to the single event upsets (SEU) in sequential logic, the single event transients (SET) in combinational logic and the single event latchup (SEL). The dual modular redundancy (DMR) and a SEL power-switch (SPS) are the basis for a modified ASIC design flow. Measurement results have proven the correct functionality of DMR and SPS circuits, as well as a high fault tolerance of implemented ASICs along with moderate overhead in respect of power consumption and occupied silicon area. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown

    Publication Year: 2012 , Page(s): 12 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (699 KB) |  | HTML iconHTML  

    Because of the aggressive scaling into the nanometer regime, degradation due to wearout significantly impairs design parameters. For instance, such wearout is caused by gate oxide breakdown, which decreases the operating lifetime of integrated circuits to an extent that cannot be neglected by circuit designers to date. In this paper, we introduce an approach which applies selective redundancy to different combinational designs in order to improve reliability as regards gate oxide breakdown. Therefore, the most vulnerable transistor stacks of standard cells are doubled based on activity and the propagation delay of the design. Finally, reliability improvements of up to 75% are presented that are gained with Spice simulations. Such improvements come at the price of overhead for area and power consumption as well as delay of at most 14%. However, it is interesting to notice that the initial delay penalty of our enhanced designs finally turn into a timing advantage, as the designs are more and more affected by wearout over time. Hence, this advantage translates into further reliability improvements when clock requirements are also considered. Besides, it needs to be noted that the presented strategies can additionally improve defect yield. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of Petri nets into FPGA with operation flexible memories

    Publication Year: 2012 , Page(s): 16 - 21
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (585 KB) |  | HTML iconHTML  

    In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into distributed and flexible memory. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An evaluation of the application dependent FPGA test method

    Publication Year: 2012 , Page(s): 22 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems

    Publication Year: 2012 , Page(s): 26 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (498 KB) |  | HTML iconHTML  

    Providing low power consumption, high throughput and flexible solution is a challenge during designing process of a mobile software defined radio (SDR) system. The need for simple software generation using common programming tools becomes also a very significant factor. The paper presents the design and implementation of a chip multithreading general-purpose processor core (GPP), as the first step towards designing a flexible and programmer friendly SDR processor platform. Software tools developed for the hardware are described. The future work will be focused on designing tightly-coupled coprocessor extensions (TCC) for an application specific digital signal processing (DSP) purposes. AGATE processor system is described in form of a highly configurable library using Verilog language. The concept verification process was performed on the Xilinx Virtex-6 ML605 FPGA evaluation board. The maximum achieved frequency for the 8-thread processor is 190 MHz. Gate level simulation along with Value Change Dump (VCD) power estimation analysis were performed using three CMOS technologies: 130 nm, 90 nm and 65 nm. AGATE is capable of performing up to 0.72 DMIPS/MHz/thread with the maximum frequency of over 700 MHz and the power consumption of about 3 mW/core using 65 nm process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improving the iterative power of resynthesis

    Publication Year: 2012 , Page(s): 30 - 33
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (850 KB) |  | HTML iconHTML  

    We present a method of improving the iterative power of resynthesis of Boolean networks in this paper. In principle it is based on iterative resynthesis of parts of the network, instead of processing the network as a whole. The parts are randomly selected, thus more variability is introduced. The process is scalable, at least as much as the state-of-the-art. We show that our method performs better than the academic state-of-the-art, the ABC tool from Berkeley. This is documented by extensive experiments on LGSynth'93 benchmark circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NAND/NOR gate polymorphism in low temperature environment

    Publication Year: 2012 , Page(s): 34 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (642 KB) |  | HTML iconHTML  

    The fundamental aspect behind this paper is focused on behaviour of polymorphic digital circuits in potentially harsh operating environment. The area of polymorphic electronics takes and an advantage of inherently built-in features that open up the possibility for on-the-fly adjustment of a particular circuit function with respect to the environment. The most prevalent benefit here is connected with the fact that space-efficient circuit implementation can be achieved due to the adoption of polymorphic principles and, thus, eliminate the need for an additional function change controller. The experimental setup was based around reconfigurable polymorphic chip REPOMO32, which is primarily designed to be configured (in addition to the configuration bit stream) by means of using the level of power supply voltage (Vdd), and carrier board with all necessary capabilities for temperature measurement up to -40C boundary and its response analysis. Experiments clearly indicate that polymorphic gates in the chip can be easily controlled not only by Vdd, but also by temperature. The obtained results also prove that the physical design of the REPOMO32 chip is robust enough under wide range f operating temperature. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Current sensing completion detection in dual-rail asynchronous systems

    Publication Year: 2012 , Page(s): 38 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents the fundamental background of the completion methodology, detailed explanation of the sensing circuitry operation, achieved simulation results as well as the comparison to state-of-the-art methods of completion detection. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST

    Publication Year: 2012 , Page(s): 42 - 45
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    This paper presents a novel approach for selecting optimal pseudo random and deterministic test patterns and minimizing test time for multi-clock domain SoCs based on a hybrid BIST architecture for each core. For test scheduling, a concurrent method considering peak power upper bound is used. A test scheduling graph is presented for modeling concurrent hybrid BIST test scheduling. Furthermore, a heuristic is proposed for selecting cores to be tested concurrently and the order of applying sequence of test patterns to each core. Experimental results show that the proposed heuristics for both selecting groups of cores to be tested concurrently during the SoC test process, and determining the amount of deterministic and pseudo random test patterns for each core, give us an optimized method for multi clock domain SoC testing compared with the existing methods. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-overhead monitoring ring interconnect for MPSoC parameter optimization

    Publication Year: 2012 , Page(s): 46 - 49
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB) |  | HTML iconHTML  

    MPSoCs need to integrate self-x properties in order to get rid of the worst-case design style which is no longer affordable in large SoCs. Integrating self-x properties in SoCs is possible through a monitoring interconnect which carries monitor information to evaluators that decide on actions that will tune the SoC operation mode. We have designed a customized interconnect for SoC monitoring/actuation. We have implemented it in VHDL and tested it in FPGA. The prototype proved that this customized interconnect provides good results regarding latency and area overheads and is a key component in enabling self-optimization in our FPGA MPSoC prototype. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs

    Publication Year: 2012 , Page(s): 50 - 55
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (661 KB) |  | HTML iconHTML  

    Reconfigurable hardware allows application specific customization of soft microprocessors. Techniques such as removing unused instructions, software emulation of instructions, custom instruction set extensions, and run-time reconfigurable instructions have been suggested. However, the techniques have largely been studied separately from each other. The contribution of this paper is a classification method enabling integration of these techniques. This allows for generating an application specific microprocessor based system from a given program. The generated microprocessor is optimized with respect to performance per area. The improvement of our methodology is demonstrated for the CoreBench benchmark. The benefit of combining the removal of unused instructions (ISA subsetting) with software emulation of rarely used instructions is shown to increase performance while at the same time reducing resource requirements. Improvement in both area and performance is accomplished thorough simplifying the design allowing an increase in clock frequency for the synthesized soft CPU. Optimizing only by using custom instructions allowed a 12% increase in performance, but also increased resource usage by 6%. Software emulation combined with ISA subsetting allowed area savings of 7%, but only improved performance by 3%. By combining custom instructions, software emulation and ISA subsetting, we achieved an performance improvement of 15% while at the same time reducing resource requirements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip

    Publication Year: 2012 , Page(s): 56 - 61
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (550 KB) |  | HTML iconHTML  

    Requirements for rapid turnaround development of complex multi-core Systems-on-Chip nowadays have advanced to the level at which a number of different in principle validation techniques have to be performed in short time. Quite common are hybrids of passive debugging of Systems-on-Chip and event-driven active verification. On top of these, we present a novel highly flexible verification infrastructure, in which parameters of monitoring can be accessible in real-time while the measurement itself is being performed. Instead of simply observing components under development, the proposed infrastructure enables the designer to interact, monitor and adjust in real-time system parameters or application software. This paper explores different microarchitecture alternatives to efficiently support flexible real-time monitoring via hardware configurable monitors which can provide abstractions of the information. A quantitative evaluation of the proposed methodology on a system-on-FPGA provides results that can serve as guidelines for system-level designers, proving the need for flexible and at the same time efficient filters for real-time monitors inside complex multi-core SoCs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.