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Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on

Date 18-20 April 2012

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Displaying Results 1 - 25 of 95
  • IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Cover

    Publication Year: 2012, Page(s):c1 - c4
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  • Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) [Title page]

    Publication Year: 2012, Page(s): 1
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  • 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) [Copyright notice]

    Publication Year: 2012, Page(s): 1
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  • Foreword to the 15th IEEE DDECS Symposium

    Publication Year: 2012, Page(s): 1
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  • Symposium committees

    Publication Year: 2012, Page(s): 1
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  • Table of contents

    Publication Year: 2012, Page(s):1 - 6
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  • On-line test of embedded systems: Which role for functional test?

    Publication Year: 2012, Page(s): 1
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  • TSV based 3D stacked ICs: Opportunities and challenges

    Publication Year: 2012, Page(s): 2
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  • Vertical Slit Transistor based Integrated Circuits (VeSTICs)

    Publication Year: 2012, Page(s): 3
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  • 3D integration: Opportunities, design challenges and approaches

    Publication Year: 2012, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (75 KB) | HTML iconHTML

    Summary form only given. More than Moore technologies like 3D-integration enable the dense integration of different circuits. With the right partitioning of functional units in a die stack; the system performance can be increased and the power consumption reduced. Design of 3D-integrated systems requests the consideration of several electrical and multi-physical interactions in a stack, e.g. therm... View full abstract»

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  • Asynchronous circuit design: From basics to practical applications

    Publication Year: 2012, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (75 KB) | HTML iconHTML

    After motivating asynchronous techniques in general, the main advantages and disadvantages will be discussed. Several asynchronous timing models such as delay insensitive (DI) quasi delay insensitive (QDI) and speed independent (SI) will be presented and compared. Completion-detection methods used in asynchronous design are reviewed. View full abstract»

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  • Automated synthesis and design-error repair of systems

    Publication Year: 2012, Page(s): 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB) | HTML iconHTML

    Due to the ever increasing complexity of digital systems, the need for formal verification methods has also been increasing steadily. Verification usually requires some form of specification. Having available a formal specification for a system, one can ask why designers have to bother fixing errors that have been detected. Or, going one step further, why not synthesize the entire system from the ... View full abstract»

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  • Fault management in an IEEE P1687 (IJTAG) environment

    Publication Year: 2012, Page(s): 7
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (78 KB) | HTML iconHTML

    Summary form only given. To meet the constant demand for performance, it is increasingly common with multi-processor system-on-chips (MPSoCs). As these integrated circuits (ICs) may contain billions of transistors squeezed on a few square centimeters, it is difficult to ensure that they are correct. Defects may escape manufacturing test or develop during operation and, further, ICs manufactured in... View full abstract»

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  • Design methodology for fault tolerant ASICs

    Publication Year: 2012, Page(s):8 - 11
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (946 KB) | HTML iconHTML

    The sensitivity of application specific integrated circuits (ASICs) to the single event effects (SEE) can induce failures of the systems which are exposed to increased radiation levels in the space and on the ground. This paper presents a design methodology for a full fault tolerant ASIC that is immune to the single event upsets (SEU) in sequential logic, the single event transients (SET) in combi... View full abstract»

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  • Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown

    Publication Year: 2012, Page(s):12 - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (699 KB) | HTML iconHTML

    Because of the aggressive scaling into the nanometer regime, degradation due to wearout significantly impairs design parameters. For instance, such wearout is caused by gate oxide breakdown, which decreases the operating lifetime of integrated circuits to an extent that cannot be neglected by circuit designers to date. In this paper, we introduce an approach which applies selective redundancy to d... View full abstract»

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  • Synthesis of Petri nets into FPGA with operation flexible memories

    Publication Year: 2012, Page(s):16 - 21
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB) | HTML iconHTML

    In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into dist... View full abstract»

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  • An evaluation of the application dependent FPGA test method

    Publication Year: 2012, Page(s):22 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (273 KB) | HTML iconHTML

    In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to chan... View full abstract»

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  • AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems

    Publication Year: 2012, Page(s):26 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (498 KB) | HTML iconHTML

    Providing low power consumption, high throughput and flexible solution is a challenge during designing process of a mobile software defined radio (SDR) system. The need for simple software generation using common programming tools becomes also a very significant factor. The paper presents the design and implementation of a chip multithreading general-purpose processor core (GPP), as the first step... View full abstract»

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  • Improving the iterative power of resynthesis

    Publication Year: 2012, Page(s):30 - 33
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (850 KB) | HTML iconHTML

    We present a method of improving the iterative power of resynthesis of Boolean networks in this paper. In principle it is based on iterative resynthesis of parts of the network, instead of processing the network as a whole. The parts are randomly selected, thus more variability is introduced. The process is scalable, at least as much as the state-of-the-art. We show that our method performs better... View full abstract»

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  • NAND/NOR gate polymorphism in low temperature environment

    Publication Year: 2012, Page(s):34 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (642 KB) | HTML iconHTML

    The fundamental aspect behind this paper is focused on behaviour of polymorphic digital circuits in potentially harsh operating environment. The area of polymorphic electronics takes and an advantage of inherently built-in features that open up the possibility for on-the-fly adjustment of a particular circuit function with respect to the environment. The most prevalent benefit here is connected wi... View full abstract»

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  • Current sensing completion detection in dual-rail asynchronous systems

    Publication Year: 2012, Page(s):38 - 41
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents th... View full abstract»

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  • Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST

    Publication Year: 2012, Page(s):42 - 45
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (431 KB) | HTML iconHTML

    This paper presents a novel approach for selecting optimal pseudo random and deterministic test patterns and minimizing test time for multi-clock domain SoCs based on a hybrid BIST architecture for each core. For test scheduling, a concurrent method considering peak power upper bound is used. A test scheduling graph is presented for modeling concurrent hybrid BIST test scheduling. Furthermore, a h... View full abstract»

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  • A low-overhead monitoring ring interconnect for MPSoC parameter optimization

    Publication Year: 2012, Page(s):46 - 49
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    MPSoCs need to integrate self-x properties in order to get rid of the worst-case design style which is no longer affordable in large SoCs. Integrating self-x properties in SoCs is possible through a monitoring interconnect which carries monitor information to evaluators that decide on actions that will tune the SoC operation mode. We have designed a customized interconnect for SoC monitoring/actua... View full abstract»

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  • Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs

    Publication Year: 2012, Page(s):50 - 55
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (661 KB) | HTML iconHTML

    Reconfigurable hardware allows application specific customization of soft microprocessors. Techniques such as removing unused instructions, software emulation of instructions, custom instruction set extensions, and run-time reconfigurable instructions have been suggested. However, the techniques have largely been studied separately from each other. The contribution of this paper is a classificatio... View full abstract»

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  • An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip

    Publication Year: 2012, Page(s):56 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (550 KB) | HTML iconHTML

    Requirements for rapid turnaround development of complex multi-core Systems-on-Chip nowadays have advanced to the level at which a number of different in principle validation techniques have to be performed in short time. Quite common are hybrids of passive debugging of Systems-on-Chip and event-driven active verification. On top of these, we present a novel highly flexible verification infrastruc... View full abstract»

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