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Microelectronic Test Structures (ICMTS), 2012 IEEE International Conference on

Date 19-22 March 2012

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Displaying Results 1 - 25 of 61
  • [Front matter]

    Publication Year: 2012 , Page(s): 1 - 4
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  • Table of contents

    Publication Year: 2012 , Page(s): 1 - 6
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  • Session 1: Design margin

    Publication Year: 2012 , Page(s): 1 - 2
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  • Ring oscillator with calibration circuit for accurate on-chip IR-drop measurement

    Publication Year: 2012 , Page(s): 3 - 8
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1623 KB) |  | HTML iconHTML  

    Resource estimation of power distribution network (PDN) is a critical issue for the resource management of LSIs. To evaluate the impact of PDN parameters to the quality of power distribution, an accurate PDN simulation model is necessary. To reflect the real silicon's behavior to PDN simulation models, we propose a test structure that consists of an array of Ring Oscillators (ROs) with calibration circuits for static IR-drop measurement. The calibration circuit is used for the estimation of the RO frequency at no IR-drop condition so that we can estimate the absolute value of the IR-drop under operating condition. A test chip which includes 540 ROs and 270 calibration circuits is fabricated in a 65 nm process. The maximum discrepancy between the measurement and simulation values is 0.18 % in our experiment. View full abstract»

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  • Calibration of library element optimization to improve static power

    Publication Year: 2012 , Page(s): 9 - 13
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (743 KB) |  | HTML iconHTML  

    Library elements (or standard cells) are basic building blocks of integrated circuits. These are built early in the technology cycle. Small changes to library elements can result in significant power/performance changes to large designs instantiating them. Qualifying these small changes on silicon can benefit products. Several physical layout optimizations are performed to improve performance and/or reduce standby power. This paper demonstrates the application of ring oscillators to calibrate such optimizations. These ring oscillators are designed to provide cell-specific validation and feedback to the entire library optimization. Silicon calibration results from 55nm technology node are discussed. View full abstract»

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  • A novel structure of MOSFET array to measure off-leakage current with high accuracy

    Publication Year: 2012 , Page(s): 14 - 17
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1734 KB) |  | HTML iconHTML  

    We developed a new test structure consisting of a MOSFET array that can accurately measure off-leakage current (Ioff). The features of this structure are that MOSFETs' source and drain are directly connected to probing pads and that each pair of source and drain terminals is unshared to avoid Ioff contamination by untargeted MOSFETs. The structure is implemented in scribe lines for the 90 nm technology node and beyond, and the measurements of MOSFET characteristics for the array and non-array structures are well correlated. View full abstract»

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  • A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch

    Publication Year: 2012 , Page(s): 18 - 22
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    To validate our optimized design theory for Even Stage Ring Oscillators (ESROs), we have developed a Universal ESRO TEG (U-ESRO TEG) constructed with Equivalent Variable-W Transistors (EVWTs) and Initial-voltage Preset-able Inverters (IPIs). The design parameters can be changed with a single circuit, and it is possible to measure the operation margin and oscillation availability of an ESRO. Experimental results confirm the validity of our ESRO design theory. View full abstract»

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  • Session 2: Variability

    Publication Year: 2012 , Page(s): 23 - 24
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  • Inhomogeneous ring oscillator for WID variability and RTN characterization

    Publication Year: 2012 , Page(s): 25 - 30
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (991 KB) |  | HTML iconHTML  

    We propose an inhomogeneous ring oscillator (RO) whose performance is strongly influenced by a small set of transistors for characterizing transistor-by-transistor variability. Performance sensitivities of the transistors are enhanced by inserting a “singular point” into a homogeneous RO. Proposed ROs have been embedded in a 65nm RO-array test structure, and it is verified that the proposed ROs are highly sensitive to Within-Die (WID) local variability and Random Telegraph Noise (RTN). The amounts of random variation in threshold voltages(VthN and VthP) and channel length(L) are extracted from the WID frequency variation. Temporal variation of oscillation frequency due to RTN is observed in the inhomogeneous RO. View full abstract»

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  • Addressable test structures for MOSFET variability analysis

    Publication Year: 2012 , Page(s): 31 - 35
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1238 KB) |  | HTML iconHTML  

    Aggressive scaling of CMOS transistors has increased variations in threshold voltages, drive currents and gains. In order to meet circuit performance targets, the designer requires detailed knowledge of variability to enable manufacturable products. This paper presents a 4-bit addressable array-based test structure with a centre reference transistor allowing evaluation of variability in advanced technologies. We demonstrate a method of verifying the region in which the measurements of transistors in the array are valid. View full abstract»

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  • Test structures for interdie variations monitoring in presence of statistical random variability

    Publication Year: 2012 , Page(s): 36 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1664 KB) |  | HTML iconHTML  

    We study the limitations of single transistor test structures for Process Variations monitoring in presence of statistical random variability, and compare them with transistor array structures in 45 CMOS technology. By optimizing transistor array design considering statistical variability, layout effects, and interconnect parasitics, we first estimate and then verify on silicon that x5 reduction of statistical variability and excellent correlation with ring oscillator frequency that can be reached for array structure. Transistor arrays are demonstrated to be well suited for monitoring impact of process variations, whether it is die-to-die, or wafer-to-wafer. View full abstract»

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  • Session 3: MEMS

    Publication Year: 2012 , Page(s): 43 - 44
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  • Piezoresistive membrane deflection test structure for the evaluation of hermeticity in low cavity volume MEMS and microelectronic packages

    Publication Year: 2012 , Page(s): 45 - 49
    Cited by:  Papers (1)
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    This paper details the design, fabrication and characterisation of a piezoresistive membrane deflection test structure for the electrical evaluation of hermeticity in low cavity volume package. This test structure uses the 0-level silicon cap, defined in the MultiMEMS foundry service, as a deflecting membrane to electrically monitor changes in package cavity pressure over time. The hermeticity of the package can then be determined in real-time and low leak rates can be measured using a pressurisation stage, which also accelerates the test. The minimum detectable leak rate of the test structure without test acceleration is 6.9×10-12 atm.cm3.s-1, which is two orders of magnitude lower than the limit of the traditional helium fine leak test method. View full abstract»

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  • A diaphragm based piezoelectric AlN film quality test structure

    Publication Year: 2012 , Page(s): 50 - 54
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    Aluminum nitride (AlN) is becoming a commonly used piezoelectric material for various applications due to its compatibility with CMOS processing. However, the piezoelectric properties of AlN are highly dependent on the deposition process and the underlying layers, and typically require several test structures in order to determine the quality of the film. This paper highlights a MEMS based diaphragm test structure which allows various types of material characterization to be tested, in order to determine the quality of the AlN film on a bulk micromachined device wafer. View full abstract»

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  • A novel high-throughput on-wafer electromechanical sensitivity characterization system for piezoresistive cantilevers

    Publication Year: 2012 , Page(s): 55 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1139 KB) |  | HTML iconHTML  

    In this work we present the development of a new set-up that allows on-wafer sensitivity characterization of piezoresistive cantilevers. In this way we reduce considerably the testing time compared to the techniques available up to date but at the same time we maintain a high measurement precision. Moreover it can be easily used for characterization of broad types of batch fabricated micro- and nanoelectromechanical systems (MEMS and NEMS). Together with the sensitivity measurement we present also the methods to test the cantilever spring constant and the electrical noise. Using these techniques we measured the performance of multiple piezoresistive cantilevers in two wafers and from these values we extracted important fabrication materials parameters such as Young modulus, Hooge and piezoresistive factors. View full abstract»

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  • Modification and characterisation of material hydrophobicity for surface acoustic wave driven microfluidics

    Publication Year: 2012 , Page(s): 61 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (979 KB) |  | HTML iconHTML  

    Surface acoustic waves (SAW) generated in a piezoelectric substrate may be used to manipulate micro-scale droplets of liquid in a digital microfluidic system for lab-on-a-chip applications. The wettability of the surface over which a droplet is driven determines the ease and speed with which the droplet is propelled. This provides the opportunity to achieve fine control of SAW driven droplets simply by patterning of the surface into areas with different levels of wettability. This paper evaluates a number of different materials and surface preparation techniques and assesses their manufacturability and efficacy for this application. Test structures have been designed and developed to help optimise a fabrication process using the biocompatible polymer Parylene. Early results obtained using airflow as a driving force show that it is possible to manipulate droplets through direction changes of up to 60°. Additional work has been done using surface acoustic waves as the driving force to determine the extent to which droplets can be guided to desired locations. View full abstract»

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  • A blur-range test structure of collimation-controller-integrated silicon shadow mask for three-dimensional surface patterning with sputtering

    Publication Year: 2012 , Page(s): 66 - 70
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    This paper proposes a test structure for development of collimation-controller-integrated three-dimensional shadow mask to control pattern blurs by isotropic deposition such as sputtering. The collimator was intelligently employed to both suppress and intentionally introduce the blurring, depending on the substrate position. Consequently, we have successfully patterned Titanium electrodes over 225μm-deep, 720μm-wide trenches by 15μm-wide gaps, which have not been obtainable with standard 3-D shadow mask. The purpose of the test structure is to quantify blurring range by collimator to optimize its aperture widths to control deposition angles by mask design. Clear relationship between blur-range and the gap was observed and shown to be predictable by its geometry (similitude of triangles). View full abstract»

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  • Session 4: Poster session

    Publication Year: 2012 , Page(s): 71 - 72
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  • Study on Device Matrix Array structure for MOSFET gm variability evaluation

    Publication Year: 2012 , Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (906 KB) |  | HTML iconHTML  

    The effect of Device Matrix Array structure on MOSFET gm-variability measurement is studied. One of the two transfer gates, which are connected to an MOSFET source terminal for both Kelvin measurement and addressable access, is removed. This modification enables us to measure and to reduce the effect of the metal wiring resistance on Kelvin measurement, and thus to estimate the intrinsic MOSFET gm-variability. View full abstract»

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  • A proposition on test circuit structures using selectively metal-covered transistors for a laser irradiation failure analysis

    Publication Year: 2012 , Page(s): 77 - 81
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    A quick and easy laser experiment for photocurrent induced failure investigations has been described. In order to focus a laser beam on a desired transistor in complex LSI circuits, novel test circuit structures using selectively metal-covered transistors have been proposed. Photocurrent induced failures have been successfully observed in a target CMOS inverter with an SR Flip Flop detector. The laser irradiation failures have also been observed in a selectively metal-covered CMOS SRAM test cell. View full abstract»

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  • Threshold voltage variation extracted from MOSFET C-V curves by charge-based capacitance measurement

    Publication Year: 2012 , Page(s): 82 - 86
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1569 KB) |  | HTML iconHTML  

    The threshold voltage variations for the MOSFETs having various channel structures are evaluated from their measured capacitance-voltage (C-V) curves. It is found that they show reasonable dependence on the channel structure and smaller than those evaluated from the current-voltage (I-V) relations. As one of the reasons that the difference of between the variations extracted from C-V curves and those extracted from I-V relations arises, it is considered that the local channel dopant fluctuation increases the current variation. Furthermore, it is found that the evaluated flat-band voltage variations represent the reasonable behavior. View full abstract»

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  • Electrical characterisation of dry microneedle electrodes for portable bio-potential recording applications

    Publication Year: 2012 , Page(s): 87 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (915 KB) |  | HTML iconHTML  

    Electrically stable electrodes are required for personal healthcare monitoring systems in order to monitor vital parameters without affecting patient lifestyle. This paper presents the electrical characterization of MEMS-based microneedle electrodes for surface bio-potential recording. Electrical measurements are presented for the impedance and DC offset of the electrodes and typical bio-potential signal (ECG, EMG) recordings are illustrated using the electrodes. These results demonstrate the suitability of the new electrodes for long-term wearable recording applications. View full abstract»

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  • Reliability analysis of NAND gates with modified channel length in series n-MOSFETs

    Publication Year: 2012 , Page(s): 91 - 94
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    A channel length engineering technique for optimization of primitive cells in standard cell libraries is effective for a leakage reduction method without significant increase of delay time, maintaining the same cell size. Reliability of NAND gates with series n-MOSFETs, which have modified channel length, have been analyzed under voltage stress condition with a test structure of ring oscillator implemented in standard 90 nm CMOS process. Stress time tstrs dependence of degradation ratio of delay time td and operation current IOP follow a power law of tstrs. A channel length modification from 0.10 to 0.11 μm for the topmost n-MOSFET in series connected MOSFETs of NAND gates provides not only leakage current reduction but reliability improvement with less performance degradation under high voltage stress condition. View full abstract»

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  • A novel high accurate analytical technique of the leak current for the product chip

    Publication Year: 2012 , Page(s): 95 - 97
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    We propose the novel technique to analyze the leak current of the product chip accurately. Comparison of calculated and measured leak current proves the validity of this technique. The small variation causation of the product's leak current is able to be analyzed. Moreover, leak current reduction guide is obtained with the detail component factor analysis. Applying to the in-line monitor, all wafers could be an analytical object. View full abstract»

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  • Simple gate charge (Qg) measurement technique for on-wafer statistical monitoring and modeling of power semiconductor devices

    Publication Year: 2012 , Page(s): 98 - 100
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (923 KB) |  | HTML iconHTML  

    Conventional measurement techniques for gate charge (Qg) require large array test-structures and additional circuitry. These techniques do not use standard ET test equipment, require careful calibration, and are expensive in terms of silicon area. Hence they are not amenable to on-wafer measurement. In this paper, we present a simple yet accurate CV method for on-wafer measurement and monitoring of gate charge. Based on the principle that Q = ∫Idt = ∫CdV, this technique uses small PCM test-structures and basic ET equipment (LCR meter), yet is accurate to within 2%, and thus enables statistical on-wafer process monitoring of Qg. View full abstract»

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