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Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th

Date 7-9 Dec. 2011

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Displaying Results 1 - 25 of 165
  • 2011 IEEE 13th Electronics Packaging Technology Conference [front matter]

    Publication Year: 2011 , Page(s): 1 - 20
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  • Large Cu wire wedge bonding process for power devices

    Publication Year: 2011 , Page(s): 1 - 5
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1507 KB) |  | HTML iconHTML  

    Due to the high cost of gold, Cu-wire bonding is being used more and more on fine-pitch, high-pin-count IC devices. Medium-size Cu wire (>;1mil) has been used for bonding on power devices for years but has not become a popular interconnect option. Recently, however, successful bonding of large (16-mil) Cu wire on specifically metallized IGBTs was reported. Some of these devices showed 10 times the power-cycling life-span of standard Al wire bonded to Al die metallization. In order to develop and make this process production capable, K&S has developed a new Cu bond head that delivers bond forces, wire clamp forces, and ultrasonic power that are significantly higher than those typically achieved with Al wire. This rear-cut head is compatible with most current power-module designs. A modified V-groove bond tool for use with the new head enables bond shear and pull strengths that are 1.0 and 1.5 times the wire's tensile strength respectively. View full abstract»

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  • Cu wire bonding for fine pitch 40nm circuit under pad silicon integrated circuits: Development of a comprehensive robust Cu wire bonding process

    Publication Year: 2011 , Page(s): 6 - 11
    Cited by:  Papers (2)
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    Historically Cu wire has been targeted to lower pin count high power discrete devices and consumer product for a long time. As gold costs increased the industry started focusing on moving more mainstream products to Cu wire. Markets that have seen the largest growth in Cu wire bonded products include consumer electronics, communication devices and industrial electronics etc. However, Cu wire has been used sparingly in high reliability markets which require stringent and extensive reliability performance. One of the reasons is that the leading edge silicon nodes with low-k/ELK device bonding pads are vulnerable to damage during wire bond process even with gold wire. In this manuscript our work on the development of a comprehensive protocol, experimental procedure and exhaustive characterization of a highly reliable Cu wire bonding process and bill of materials for use on wire bond devices made in leading edge silicon node technologies is summarized. Included in the work was the application of this development process to multiple aspects of the overall process and materials selection including but not limited to: i) Cu wire bond process development at five different manufacturing locations owned by three different assembly suppliers; ii) three different mold compounds; iii) three different package types; and iv) multiple integrated circuit designs, all with circuit under pad. Also summarized are the extensive reliability evaluations that were completed through the course of this work. Using these exhaustive protocols, experimental procedures, characterizations and reliability studies, we successfully developed a robust bond pad design, which in combination with the wire bond process and bill of materials results in highly reliable Cu wire bonded devices in advanced silicon technology nodes. View full abstract»

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  • Bondability of copper wires on PPF leadframe

    Publication Year: 2011 , Page(s): 12 - 19
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    The imposition of lead-free production for most of electrical and electronic components in the 2006 EU legislation has lead to leadframes manufacturers looking into other solderable alternatives for PCB soldering assembly. One of the alternatives is Tin (Sn) plating but it brings along other risks such as whisker growth. Nickel palladium (NiPd) based PPF (Pre-Plated Finishes) leadframe becomes another feasible option with no Sn-whisker risk. This introduction has greatly economized the cost of IC assembly by eliminating the post-mold plating process. View full abstract»

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  • Copper wirebond pull test and reliability characterization with finite element simulation

    Publication Year: 2011 , Page(s): 20 - 24
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    In this paper, we will compare Cu wire and Au wire behavior during pull test and package reliability test through thermo-mechanical simulation. Relationship between wire pull test and package reliability test, i.e. thermal cycling, is also evaluated in term of die stress underneath the wire bond pad area. A new stress index concept is proposed to characterize the overall die stress level underneath bond pad. Based on this concept, a new method to evaluate Cu pull test limit is established with benchmark to current Au wire standard. The methodology is demonstrated through a Cu wire bonded power package, with the extensive work of process development, reliability test, and stress simulation etc. View full abstract»

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  • Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging

    Publication Year: 2011 , Page(s): 25 - 28
    Cited by:  Papers (2)
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    In this paper, we report on the development of Cu pillars and their impact on the subsequent thinning process for 3D applications. As the Cu pillars have a height of tens of microns (typically between 50-100μm), controlling the total thickness variation (TTV) after wafer thinning is becoming even more challenging. The Cu pillars are processed after completion of the Back End of Line (BEOL) with a target thickness of 50μm for a diameter of 80μm and a pitch of 200μm. The key challenge for 3D integration is the control of the wafer TTV after back grinding in order to allow TSV reveal. After optimization of the temporary wafer bonding in presence of high topography induced by 50μm high Cu pillars, a TTV after thinning below 5μm is achieved, which is comparable to the TTV obtained after wafer thinning without topography. View full abstract»

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  • Nonlinear copper behavior of TSV for 3D-IC-integration and cracking risks during BEoL-built-up

    Publication Year: 2011 , Page(s): 29 - 33
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    The application of copper-TSVs for 3D-IC-integration generates novel challenges for reliability analysis and prediction, i.e. to master multiple failure criteria for combined loading including residual stresses, interface delamination, cracking and fatigue. So, the thermal expansion mismatch between copper and silicon yields to stress situation in silicon surrounding the TSVs which is influencing the electron mobility and as a result the transient behavior of transistors. Furthermore, pumping and protrusion of copper is a challenge for Back-end of Line (BEoL) layers of advanced CMOS technologies already during manufacturing. These effects depend highly on the temperature dependent elastic-plastic behavior of TSV-copper and the residual stresses determined by the electro deposition chemistry and annealing conditions. View full abstract»

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  • Thermo-mechanical impact of the underfill-microbump interaction in 3D stacked integrated circuits

    Publication Year: 2011 , Page(s): 34 - 38
    Cited by:  Papers (4)
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    This paper focuses on stress generated in Si dies as a consequence of the interaction mechanism of the underfill material and microbumps in 3D stacked integrated circuits (ICs). The impact of the mechanism is simulated by means of finite element modeling (FEM) and verified by electrical measurements. Furthermore, a FEM study is employed in order to provide proposals for stress reduction in the active Si area due to stacking. In result, guidelines for the choice of underfill material and critical dimensional parameters of 3D stacks are pointed out. View full abstract»

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  • Near term solutions for 3D packaging of high performance DRAM

    Publication Year: 2011 , Page(s): 39 - 43
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    The revolution in performance driven electronic systems continues to challenge the IC packaging industry. To enable the new generations of processors to reach their performance potential and to achieve greater memory density and bandwidth, many manufacturers have developed a number of two-die package interface formats. Effective 3D stacking of memory die elements can offer many benefits; improved performance, increased component density and greater surface area utilization. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and end product reliability. To ensure that the memory functions are able to support the increased signal speed of the new generations of memory, package developers are relying more and more on die-stack assembly techniques and process refinement. This paper briefly reviews current two-die package assembly methodologies for the high performance, synchronous dynamic random-access memory (SDRAM) and introduces, in greater detail, an innovative two-die, face-down package assembly developed specifically for the next generation center bond memory products. View full abstract»

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  • Electroless Ni-W-P alloy as a more enduring and reliable soldering metallization

    Publication Year: 2011 , Page(s): 44 - 48
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1004 KB) |  | HTML iconHTML  

    The adoption of lead-free solders accelerates interfacial reaction because they have higher melting points and higher Sn content than the conventional Pb-Sn solders. In this work, we developed a ternary electroless Ni-W-P (6~7 wt.% P, and 15~16 wt.% W) alloy to be used as the soldering metallization due to its good thermal stability. Comparison was made with the results obtained from the conventional binary Ni-P (6~7 wt.% P) metallization. X-ray diffraction was used to study the crystallization behavior of the Ni-P and Ni-W-P deposits after annealing at various temperatures. The interfacial reactions at the Ni-P/Sn-3.5Ag interface and the Ni-W-P/Sn-3.5Ag interface were investigated after reflow and aging at 200 °C. While voids were found at the Ni-P/Sn-3.5Ag interface, which has been well known and explained, no voids were found at the Ni-W-P/Sn-3.5Ag interface after prolonged aging. In addition, it was found that the Ni-W-P layer was consumed much slower than the Ni-P layer, and the growth of Ni3Sn4 is much slower at the Ni-W-P/Sn-3.5Ag interface. These finding points out a promising lead-free solder metallization that is expected to enjoy improved reliability over long term aging and multiple reflow. View full abstract»

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  • Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag bump for 3D packages

    Publication Year: 2011 , Page(s): 49 - 52
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    Interfacial microstructure and mechanical reliability of Cu pillar/Sn-3.5Ag microbumps during annealing conditions were systematically and quantitatively evaluated. The IMC growth followed a linear relationship with the square root of the annealing time, which means that the IMC growth was controlled by a diffusion mechanism. The shear strength and IMC thickness increased quadratically with annealing time at 150°C, while the amount of solder decreased. It was clearly revealed that there exist strong correlations among IMC growth kinetics, shear strength, and fracture modes in Cu/solder microbumps. View full abstract»

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  • Reliability of copper wire bonding in humidity environment

    Publication Year: 2011 , Page(s): 53 - 58
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2604 KB) |  | HTML iconHTML  

    Copper wire bonding is being developed rapidly in recent years to replace expensive gold wire for electronic packaging. However, one issue about reliability in humidity environment causes risk in its application. The copper wire-aluminum pad interface degradation usually leads to electrical open failure. Present paper studied all the 5 factors including pad finish of chip, molding compound, wire bonding parameters, copper wire type and protective gas type in wire bonding process that affect this issue. Through bond pull test at different stage of uHAST, the influence and significance degree of the factors were obtained. The pad finish was found has the most significant effect. No degradation occurred at copper-gold and copper-palladium interface. For aluminum finish, mold compound and wire bonding parameters have significant effect. Green EMC, high USG and low Search Force in wire bonding process is benefit to enhance reliability of copper wire bonding in humidity environment. Concerning the palladium coated copper wire and bare copper wire, forming protective gas of 5%H2+95%N2 and pure N2, there was no significant effect founded. So for the safe copper wire bonding application, noble metal such as gold and palladium pad finish is the best choice. If the aluminum pad is used, green EMC and optimized wire bonding parameters are necessary to guarantee the reliability. View full abstract»

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  • Addressing Delamination for Fast Development of Reliable Packages

    Publication Year: 2011 , Page(s): 59 - 62
    Cited by:  Papers (1)
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    Delamination remains a major problem for the reliability of semiconductor components. It is typically addressed with temperature cycling tests, which are rather time-consuming. The paper presents an approach to provide data for material selection in the early development phase based on adhesion measurements and simulation. The approach provides an improved base for decision and allows to reduce development times. View full abstract»

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  • Heat conduction across multiwalled carbon nanotube/graphene hybrid films

    Publication Year: 2011 , Page(s): 63 - 66
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    Chemically-reduced graphene oxide (CR-GO) was obtained by reduction of graphene oxide in solution of hydrazine hydrate and ammonium hydroxide solution. AFM and Raman spectra indicated the formation of single-layer CR-GO nanosheets. By using the drop-cast method, multi-walled carbon nanotube (MWCNT)-CR-GO hybrid film was fabricated by transferring the synthesized CR-GO onto the top surface of MWCNT arrays. The electrical and thermal conductivity of the MWCNT-CR-GO hybrid material are also investigated. It was found that the additional layer of graphene on MWNCT reduces the thermal conductance between MWCNT and graphene induced by their non-covalent interface. View full abstract»

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  • Measurement based compact thermal model creation - accurate approach to neglect inaccurate TIM conductivity data

    Publication Year: 2011 , Page(s): 67 - 72
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (742 KB) |  | HTML iconHTML  

    In this paper two possible ways are investigated to create accurate thermal models without having validated information on the thermal properties of the applied thermal interface materials. One way is the calibration of a detailed numerical thermal model based on the physical information which can be derived from experimental structure functions. In the paper we show a complete calibration procedure using a TO-220 package as an example. Another approach is the generation of dynamic compact models based on real measurements. In order to apply this approach one has to identify the junction-to-case thermal resistance of the tested package using the JEDEC JESD 51-14 standard. View full abstract»

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  • Thermal design, analysis and optimization of a power charger for hybrid or electric vehicles

    Publication Year: 2011 , Page(s): 73 - 78
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    Hybrid or electric vehicles require an on-board battery charger that converts AC to DC with high efficiency to charge the batteries. The charger should be compatible with all international power grids, should be designed for quick charging of the battery packs, and should cater to a broad range of vehicle platforms. Heat dissipation in the battery charger is usually very high. Hence, it is imperative to choose an adequate and easily adoptable cooling method to maintain the operating temperature of the electronic devices of the charger within safe limits for a reliable system. Thermal design, analysis and optimization of such a charger is presented and discussed in this paper. View full abstract»

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  • Thermal performance evaluation of a synthetic jet heat sink for electronic cooling

    Publication Year: 2011 , Page(s): 79 - 83
    Cited by:  Papers (1)
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    This paper presents a performance investigation on a highly effective heat removal technique for heat sinks in electronic cooling applications. This arrangement utilises a pulsating fluid jet mechanism known as synthetic jet, which is characterised by zero net fluid discharge through the jet orifice. The study uses an experimental rig comprising a high-frequency pulsating air jet that impinges on a heated surface to emulate the heat sink operation attached to an electronic device. The cooling characteristics of this jet are examined for a range of parametric conditions, including jet-impinging distance while evaluating the heat removal rates. The results indicate that the pulsating jet produces outstanding cooling performance at the heated surface with significant dependency of it on the jet-impinging distance. The study also assesses the interaction of a cross-flow fluid stream on the pulsed jet operation. It is observed that the cross-flow somewhat impedes the pulsed jet thermal performance. However, the pulsed jet, with or without cross flow, delivers an overall cooling ability that supersedes the standard flow-through heat sink performance. This technique provides highly enhanced surface cooling potential without incurring increased fluid pressure drop or requiring additional fluid circuit, which are significant advantages for high-powered heat sink design. View full abstract»

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  • MEMS technology on wafer-lever LED packaging

    Publication Year: 2011 , Page(s): 84 - 87
    Cited by:  Papers (3)
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    This study demonstrated a newly type technology of a wafer level packaging method for light emitting diode (LED) with aspheric lens and microlens array using microelectromechanical systems (MEMS) technology and transfer molding process. The novel packaging structure includes two components: the silicon-based packaging substrate which is formed with arrayed reflector depression and through-hole interconnects by bulk micromachining and the optical encapsulation with lens configuration that formed by transfer molding in wafer level. By this pattern transfer process, the precise alignment between lens configuration and the reflector of silicon substrate can be achieved and batch process can be realized to reduce the costs. Beside, the packaging element can be used more applications. In the study, the pattern transfer of various lens profiles was also accomplished successfully by using silicone gel as lens mold. The brightness of the packaging elements with single aspheric lens profile and high fill factor microlens array can be increased by 26% and 16%, respectively, in comparison to the case of optical encapsulation with smooth curved surface. Furthermore, the light radiation uniformity was improved effectively through 100% fill factor microlens array. Therefore, the structure can satisfy the requirements of wafer level LED packaging and improve the heat dissipation and light extraction efficiency. View full abstract»

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  • Sinter adhesive - new horizons in semiconductor packaging

    Publication Year: 2011 , Page(s): 88 - 92
    Cited by:  Papers (1)
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    Conductive adhesives provide advantageous properties for many electronics assembly applications (low processing temperatures, high flexibility) and they are green materials. However, the limited electrical and thermal conductivity of conventional conductive adhesives restrict their usage in most cases to low to medium power density packages. The novel mAgic silver sinter adhesives feature the conventional positive properties of conductive adhesives and combine them with electrical and thermal conductivity that are comparable to solder. This new development therefore provides solutions to the growing challenge of increasing power densities related to shrinkage of packages and / or increase of power. View full abstract»

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  • Design, manufacturing and packaging of high frequency micro ultrasonic transducers for medical applications

    Publication Year: 2011 , Page(s): 93 - 98
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    The challenges for the realization of a miniaturized high frequency ultrasonic transducer linear array lie in the interconnections on the fine pitch piezoceramic elements. Within the footprint the size of a needle, only peripheral interconnections can be allowed on the transducer array such that the acoustic operations on both faces of the vibrating piezoelectric elements are not obstructed. The very low maximum processing temperature allowed also poses difficulty for conventional bonding techniques. This article presents 3-dimensional packaging using spirally rolled flexible circuits, room-temperature anisotropic conductive bonding and stencil printing for the setup of a wafer-level production process flow. View full abstract»

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  • Design and fabrication of a novel monolithic integration structure for un-cooled infrared focal plane array and readout IC

    Publication Year: 2011 , Page(s): 99 - 103
    Cited by:  Papers (1)
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    In this paper, a monolithic integration structure with TSV interconnections is introduced for un-cooled infrared FPA to do easy wafer-level-package. Firstly, the challenging process for making the structure will be reviewed and identified. And then process sequence for making the TSV interconnections and RDLs and CMOS compatible surface process for IR FPA will be developed. In the end, a WLP scheme will be developed to show the benefit of easy WLP. View full abstract»

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  • Understanding the electrical transport properties of carbon nanotubes and its metal under-layers

    Publication Year: 2011 , Page(s): 104 - 107
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    Carbon nanotubes have been widely studied due to its excellent electrical, thermal and mechanical properties, showing promising applications in both active and passive components in electronic devices. However, for such devices to be developed, compatibility issues for obtaining quality carbon nanotubes with suitable underlying substrates have to be understood. In this work, a technique to study the impact of each under layer on carbon nanotubes would be discussed. Vertically aligned multiwalled carbon nanotubes are grown on patterned metal trace with suitable barrier layers. In situ electrical measurement of the nanotubes using manipulators in a field emission scanning electron microscope was performed to understand the electrical transport at each interface. View full abstract»

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  • Low standoff Chip to Wafer bonding

    Publication Year: 2011 , Page(s): 108 - 112
    Cited by:  Papers (2)
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    Industry is moving towards having module with multiple functions and capabilities in order to satisfy consumer demands. Miniaturized the package will allowed more components to pack inside the electronic gadget. A low z-foot print of the package is one of the approaches to miniaturize the package. The adoption of micro-bump solders in the chip allowed low standoff Chip to Wafer (C2W) solder interconnects. The chip used in this study is of size 12mm × 12mm × 0.07mm and consists of array of micro-solder bumps at 80μm pitch and 50μm UBM diameter. The wafer is of 200mm diameter and 0.7mm thick. Thermal compression process was adopted to form the solder joint between the chip and wafer. The chip and wafer were subjected to thermal and pressure loading during the thermal compression process. The thermal compression approach ensured that the chip was firmly secured to the wafer before moving to other bonding site on the wafer. This avoids the issue of die shifting during the subsequent bonding process. Several chips can stacked on top of each other as the electrical interconnects can be routed through the use of through silicon vias and double-side Re-route distribution layers (RDL) on the chip. The double RDL fabrication process of the chip involved subjected the micro-bump to several thermal heats. The integrity of the micro-solder bump may be affected by the heat. Thin layer of nickel between the copper bump and solder is necessary to prevent the solder from becoming intermetallic compound before the C2W process. The developed C2W process successfully demonstrated a low standoff micro-bump chip to wafer interconnects. View full abstract»

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  • Thin wafer processing - yield enhancement through integrated metrology

    Publication Year: 2011 , Page(s): 113 - 116
    Cited by:  Papers (2)
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    Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM). Yield is the most important consideration for the transfer to HVM. At this point of the manufacturing flow the device wafers have seen complete front end processing and have a significant inherent value. Furthermore, wafer breakage does not only destroy the wafer, but it might be necessary to take the production tool down for chamber cleaning. However, wafer breakage itself is not the only concern. Defects at the wafer edge can nucleate micro cracks in the die, which can result in device failure at a later point of time. In this paper the potential defects during thin wafer processing are reviewed. A new integrated metrology module is presented, which allows 100% in-line inspection with full wafer scanning. View full abstract»

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  • Cost effective 300mm large scale eWLB (embedded Wafer Level BGA) technology

    Publication Year: 2011 , Page(s): 117 - 121
    Cited by:  Papers (1)
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    This paper will highlight some of the recent advancements in 300mm eWLB wafer development. Compared to 200mm case, 300mm eWLB wafer has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100~150% more warpage with 300mm eWLB wafer compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper also presents study of process optimization for 300mm eWLB and on overall warpage behavior in different process steps. Finally 300mm eWLB test vehicles are fabricated and tested in JEDEC standard test conditions. It also describes mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps. View full abstract»

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