By Topic

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Date 19-23 Feb. 2012

Filter Results

Displaying Results 1 - 25 of 264
  • Index to authors

    Publication Year: 2012 , Page(s): 519 - 523
    Save to Project icon | Request Permissions | PDF file iconPDF (167 KB)  
    Freely Available from IEEE
  • Awards

    Publication Year: 2012 , Page(s): 22 - 23
    Save to Project icon | Request Permissions | PDF file iconPDF (55 KB)  
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2012 , Page(s): 2
    Save to Project icon | Request Permissions | PDF file iconPDF (57 KB)  
    Freely Available from IEEE
  • Dedication

    Publication Year: 2012 , Page(s): 5
    Save to Project icon | Request Permissions | PDF file iconPDF (818 KB)  
    Freely Available from IEEE
  • Executive Committee

    Publication Year: 2012 , Page(s): 524
    Save to Project icon | Request Permissions | PDF file iconPDF (137 KB)  
    Freely Available from IEEE
  • Foreword

    Publication Year: 2012 , Page(s): 6
    Save to Project icon | Request Permissions | PDF file iconPDF (50 KB)  
    Freely Available from IEEE
  • International Technical Program Committee

    Publication Year: 2012 , Page(s): 525 - 526
    Save to Project icon | Request Permissions | PDF file iconPDF (94 KB)  
    Freely Available from IEEE
  • Reflections

    Publication Year: 2012 , Page(s): 4
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • Low-power analog signal processing

    Publication Year: 2012 , Page(s): 518
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (63 KB)  

    The reduction of the power consumption of all electronic functions is a continuous endeavor. This endeavor requires judicious comparison of analog and digital realizations from the point of view of performance per unit of power consumed. Analog signal processing offers the advantage that power consumption can be minimized at both very low and very high frequencies. This short course explores the limits in reduction of power consumption for important analog blocks. The first presentation defines the physical limits of supply voltages and power consumption based on present-day technologies and transistor models. The second presentation addresses the limits of amplifiers and filters. For all circuit blocks, figures of merit are derived, followed by circuit techniques to improve them. In the third presentation, new opportunities are identified to reduce the power consumption in all types of analog-to-digital converters, with emphasis on the improvement of the FOM with technology. Finally, in the fourth presentation, power minimization techniques are discussed for power management blocks such as dc-dc converters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Time table

    Publication Year: 2012 , Page(s): 528
    Save to Project icon | Request Permissions | PDF file iconPDF (63 KB)  
    Freely Available from IEEE
  • [Title page]

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (41 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2012 , Page(s): 3
    Save to Project icon | Request Permissions | PDF file iconPDF (34 KB)  
    Freely Available from IEEE
  • Tutorials

    Publication Year: 2012 , Page(s): 496 - 497
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (93 KB)  

    These tutorials discuss the following: RF mixers: analysis and design trade-offs; flash-memory based circuit, system, and platform; mobile GHz processor design techniques; wideband delta-sigma modulators; jitter: basic and advanced concepts, statistics, and applications; power management using integrated voltage regulators; digital calibration for RF transceivers; managing offset and flicker noise; and getting in touch with MEMS: the electromechanical interface. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Welcome!

    Publication Year: 2012 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (28 KB)  
    Freely Available from IEEE
  • ISSCC 2013 call for papers

    Publication Year: 2012 , Page(s): 527
    Save to Project icon | Request Permissions | PDF file iconPDF (64 KB)  
    Freely Available from IEEE
  • Flash memory — The great disruptor!

    Publication Year: 2012 , Page(s): 10 - 15
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB) |  | HTML iconHTML  

    In the past two decades Flash memory grew from a novelty technology to a powerful disruptor that has profoundly transformed consumer electronics and mobile computing. This was made possible through relentless cost reductions leveraging technology scaling through 19 generations of Flash memory in just 24 years, outpacing Moore's Law. NAND Flash, System-Flash, and multilevel cells (MLC) were critical elements in establishing the foundations for today's $25 billion Flash industry. Flash enabled, and in turn benefitted from new mega markets in digital consumer electronics, and more recently, from the ascendency of mobile phones and tablets as the ultimate convergence device for billions of consumers worldwide. The author began working in the semiconductor industry in the early 1970s and participated in the growth of the non volatile memory (NVM) industry [1], first as a device physicist, then as an entrepreneur and businessman. Section 2 of this paper provides the author's personal recollections of the key milestones and innovation breakthroughs that made Flash memory such a game changer. Section 3 describes the enormous impact that Flash memory has had on Consumer Electronics and Mobile Computing. Section 4 discusses some of the major challenges and opportunities ahead for the Flash industry. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The role of semiconductors in the energy landscape

    Publication Year: 2012 , Page(s): 16 - 21
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1701 KB) |  | HTML iconHTML  

    Semiconductor technologies, products and solutions have long played a key role in improving efficiency along the whole energy chain and the importance of this role will continually increase. The greatest future energy saving will come from the adoption of semiconductor technologies, especially in buildings, which are forecasted to consume around 50% less electricity in 2030. In this area, savings will come from three sources: more efficient appliances (with an estimated 60% reduction), intelligent lighting and HVAC (with up to 50% reduction), and increased energy-consumption consciousness at the consumer level, thanks to energy monitoring in-house systems (with up to 20% potential saving). Furthermore, the advent of the Smart Grid will contribute to energy saving and to eco-sustainability. Grid optimization, through the improved modeling and control that will be possible with the deployment of Smart Meters and Automatic Meter Infrastructures (AMI), will significantly reduce infrastructure losses. Above all, it will enable the integration of renewable sources as alternatives to traditional carbon-based sources, allowing the possibility of meeting international targets such as Europe's EU 20-20-20 target that can strongly contribute reductions in CO2 emissions and containment of global warming. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Take the expressway to go greener

    Publication Year: 2012 , Page(s): 24 - 30
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (625 KB) |  | HTML iconHTML  

    Microelectronics has evolved to save power. In fact, semiconductor technology has been in the lead in the reduction of power consumption, by facilitating energy monitoring, and the controlling and managing of energy consumption. The key product in this advance has been a less-commonly-known semiconductor device called the microcontroller. That the MCU uses very little power was demonstrated for the first time by Renesas in 2006, by operating a low-power MCU from the electricity generated by 4 lemons! Subseqently, in 2011, we succeeded in operating our latest low-power MCU for 3 hours and 45 minutes using one lemon as a power source. Yet, in the future, MCUs must evolve further to save power, in widespread applications including the "energy harvesting" environment. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sustainability in silicon and systems development

    Publication Year: 2012 , Page(s): 31 - 35
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB) |  | HTML iconHTML  

    In conclusion, the path to sustainability in high performance computing must start with solving the power limitation problem. To overcome this challenge, we need to take a holistic approach that utilizes process technology and circuit techniques, architectural techniques, and platform techniques including hardware and software co-design. Technology advances required to make exascale successful will trickle down to solving power limitations in mainstream devices such as handhelds. Going forward, we appeal to the semiconductor industry to be stewards of the planet by developing energy efficient technologies while minimizing their environmental footprint. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

    Publication Year: 2012 , Page(s): 38 - 40
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB) |  | HTML iconHTML  

    A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed for high-speed transactions to reduce power consumption of I/O and SSN noise. Dual-error detection, which adopts cyclic redundancy check (CRC) for DQ, and command address (CA) parity is designed to guarantee reliable transmission. GDDR5 memory also has DBI and CRC functions [1], but in this work, these schemes are implemented in a way that reduces area overhead and timing penalty. Besides these error-check functions, an enhanced gain buffer and a PVT-tolerant fetch scheme improve basic receiving ability. To meet the output jitter requirements of DDR4 SDRAM, the type of delay line for DLL is selected at initial stage according to data rate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

    Publication Year: 2012 , Page(s): 40 - 41
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture

    Publication Year: 2012 , Page(s): 42 - 44
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a common ground with a high-Vt latch. Hybrid LIO sense amplifier (H-LSA) is developed for robust LIO read operation at low voltage and high clock frequency. In order to reduce the die area, we develop a dummy-less 6F2 array architecture with no edge dummy array. These schemes are employed in a 1.2V 23nm 6F2 4Gb DDR3 SDRAM. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

    Publication Year: 2012 , Page(s): 44 - 46
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (777 KB) |  | HTML iconHTML  

    Mobile DRAM is widely adopted in battery-powered portable devices because of its low power. Recently, in mobile devices such as smart phones and tablet PCs, higher performance is required to support 3D gaming mode and high-quality video. These trends lead to consideration of higher-performance DRAMs than LPDDR2, while the power budget for DRAMs for mobile devices cannot increase. DRAMs with wide I/O or serial I/O have been reviewed as candidates for over 6.4GB/s channel bandwidth. However, wide-I/O DRAMs [1] must solve issues such as stacking yield for higher density and failure analysis modeling of system-in-package (SiP), and most serial I/Os have worse I/O power efficiency than LPDDR2. For an evolutionary successor of LPDDR2, therefore, we design a 1.2V 1.6Gb/s/pin ×32 4Gb low-power DDR3 SDRAM (LPDDR3) with input skew calibration and enhanced refresh control schemes, achieving 6.4GB/s total data bandwidth. Most features of LPDDR3 are backward compatible with LPDDR2, except that channel termination, command-address (CA) training, and write leveling are adopted. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

    Publication Year: 2012 , Page(s): 46 - 48
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface

    Publication Year: 2012 , Page(s): 48 - 50
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    The process variation among 512 DRAM samples is more than 30%. The performance variation of general circuits is predicted to be over 60% in 2012. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more, the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost, TSV DRAM for high-speed operation partially adopts a DLL in the master die. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.