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ASIC (ASICON), 2011 IEEE 9th International Conference on

Date 25-28 Oct. 2011

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Displaying Results 1 - 25 of 284
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Title page]

    Publication Year: 2011, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2011, Page(s): 1
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  • ASICON 2011 organization

    Publication Year: 2011, Page(s):I - VI
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  • Welcome to ASICON 2011

    Publication Year: 2011, Page(s): VII
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  • ASICON 2011 sponsorship

    Publication Year: 2011, Page(s): VIII
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  • Technical session index

    Publication Year: 2011, Page(s):X - XLV
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  • Author index

    Publication Year: 2011, Page(s):ii - xv
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  • A behavior-based reconfigurable cache for the low-power embedded processor

    Publication Year: 2011, Page(s):1 - 5
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (407 KB) | HTML iconHTML

    In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cac... View full abstract»

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  • A novel method for storage architecture of pipeline FFT processor

    Publication Year: 2011, Page(s):6 - 8
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB) | HTML iconHTML

    This paper presents a new method to improve the storage architecture of the pipeline fast Fourier transform (FFT) processor. The main idea is interpreted as follows. The FFT butterfly calculation can operate with the same reading and writing address every time. In this case, each butterfly operation unit (BFU) can read and write on the same RAM at one time. Then the pipeline purpose is achieved by... View full abstract»

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  • Design of resistant DPA three-valued counter based on SABL

    Publication Year: 2011, Page(s):9 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (866 KB) | HTML iconHTML

    Through studying the design principles of multi-valued logic circuit and the SABL circuit, this paper presents a design scheme of three-valued counter. Two-valued coding method and SABL circuit characteristics such as complementary output signals and the capacitance coupling effect are integrated to implement the developed scheme. Then, the current compensation circuit is used to keep steady outpu... View full abstract»

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  • Improvement of adiabatic domino circuits and its application in multi-valued circuits

    Publication Year: 2011, Page(s):13 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB) | HTML iconHTML

    By researching the adiabatic circuits, domino circuits and multi-valued circuits, the scheme of a low-power and high-speed ternary gate circuit was proposed. First, the adiabatic domino circuit was improved by using two-phase overlapping clocks to guarantee energy recovery to the full and enhance reliability of the circuit. Then, the basic structure of ternary gate circuit was designed based on th... View full abstract»

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  • Low power shift registers for megabits CMOS image sensors

    Publication Year: 2011, Page(s):17 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1137 KB) | HTML iconHTML

    This study investigated the design of low-power shift registers (SR) for CMOS image sensors. First we analyzed a classic clock-gating-control-unit (CGCU) based SR, and showed that besides inefficient area utilization, the CGCU SR is subject to high power consumption due to coupling noise and leakage current. In this work, we developed new design techniques called LGCS (locally gated clock signals)... View full abstract»

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  • High-parallel LDPC decoder with power gating design

    Publication Year: 2011, Page(s):21 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB) | HTML iconHTML

    Leakage power is growing comparable to dynamic power dissipation as a result of technology trends, and thus it has become an important issue in low-power circuit design. As a popular technique for standby power reduction, power gating is applied to high-parallel LDPC decoder for WiMAX standard. The clustered-block processing engine (CBPE) array are divided into 9 power domains, and they are switch... View full abstract»

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  • A reconfigurable macro-pipelined DCT/IDCT accelerator

    Publication Year: 2011, Page(s):25 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (963 KB) | HTML iconHTML

    In this paper, a reconfigurable macro-pipelined (RMP) accelerator is proposed to speed up the Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute fixed-point or floating-point, one-dimensional or multi-dimensional DCT/IDCT according to different system requirements. The prototype is implemented on Xilinx ML605 experiment boar... View full abstract»

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  • Scheduling to timing optimization for a novel high-level synthesis approach

    Publication Year: 2011, Page(s):29 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (482 KB) | HTML iconHTML

    Traditional IC design methodology based on standard cells shows its limitation on design efficiency, which can not satisfy the needs for shorter time-to-market and more advanced functionality of IC products. To solve this problem, a novel high level synthesis method named operator design method is proposed. In this paper, a scheduling scheme to timing optimization for operator design method is pro... View full abstract»

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  • High reliable digital signal processor for automotive application

    Publication Year: 2011, Page(s):33 - 34
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB) | HTML iconHTML

    Today, in automotive application, especially for safety-critical part, more and more customers request for high reliable feature. In the recent years, the international norm IEC 61508 and ISO 26262 has been adopted in many application fields as the key reference for functional safety. In this paper, a distributed fault detection based high reliable compact digital signal processor architecture is ... View full abstract»

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  • A novel Differential fault analysis on AES-128

    Publication Year: 2011, Page(s):35 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB) | HTML iconHTML

    In this paper, a novel Differential fault analysis on AES-128 is proposed to find the initial key. First, by inducing four bytes random faults into the ninth round key stored in static RAM, the relationship between faults in the last two round keys can be revealed. Then, according to the difference between the correct and corrupted ciphertext, faults induced can be determined fast. Finally, under ... View full abstract»

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  • Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU

    Publication Year: 2011, Page(s):39 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (794 KB) | HTML iconHTML

    We have applied thoroughly clock gating technique to the SH-4A FPU (Floating Point Unit) core [1] while still keeping it co-operates with CPU core. As a result, 97% flip-flops in FPU is gated. And the power consumption is saved up to 78.11% in FPU, corresponding to 17.02% power consumption reducing of total CPU and FPU core in Dhrystone benchmark. This paper introduces such approach in ... View full abstract»

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  • A hardware/software co-design approach for multiple-standard video bitstream parsing

    Publication Year: 2011, Page(s):43 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (373 KB) | HTML iconHTML

    In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstreams is analyzed. Then a hardware/software partition is proposed accordingly. Due to the high data rate, syntax elements in slice data and lower layers are commonly parsed by hardware. As fo... View full abstract»

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  • ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

    Publication Year: 2011, Page(s):47 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1200 KB) | HTML iconHTML

    This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With thi... View full abstract»

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  • Analysis of adaptive support-weight based stereo matching for hardware realization

    Publication Year: 2011, Page(s):51 - 54
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB) | HTML iconHTML

    Adaptive support-weight algorithm can generate high quality disparity map for stereo matching. But due to the complexity, it requires large internal memory size and bandwidth to meet the real-time constraint. In this paper, we first analyze the requirements of this algorithm from the hardware perspective. Then we propose our Support-Weight Window Reuse (SWWR) technique which can shorten computatio... View full abstract»

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  • A high performance sound source localization system based on macro-pipelined architecture

    Publication Year: 2011, Page(s):55 - 58
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB) | HTML iconHTML

    This paper presents a novel macro-pipelined sound source localization system . The system employs a small 4-microphone array and uses the time-delay estimation method. By exploiting the parallelism of the cross-correlation algorithm, and using a macro-pipelined structure, the proposed system achieves both high accuracy and quick response capability. To verify the solid performance of the proposed ... View full abstract»

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  • Research on design of a reconfigurable parallel structure targeted at LFSR

    Publication Year: 2011, Page(s):59 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    The paper proposed a reconfigurable parallel hardware structure targeted at linear feedback shift register. As to the reconfigurable performance, the structure could reconfigure different LFSR in various stream ciphers. As to the parallel performance, the proposed hardware structure could support parallel update of LFSR sequences in one clock cycle. Besides, with the tradeoff between the flexibili... View full abstract»

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  • Using NOC technology to improve photoelectric encoder system for LAMOST spectroscopes

    Publication Year: 2011, Page(s):64 - 66
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB) | HTML iconHTML

    Large Sky Area Multi-Object Fiber Spectroscopic Telescope (LAMOST), consists of 16 spectroscopes which have lots of motors should be controlled. This paper mainly introduces how to use Network-on-chip (NOC) technology to improve the photoelectric encoder system of LAMOST spectrometer controller via Altera Corporation's Qsys tool. Besides, a comparison of system performance in different pipeline st... View full abstract»

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