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2011 IEEE International Test Conference

20-22 Sept. 2011

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Displaying Results 1 - 25 of 76
  • [Title page]

    Publication Year: 2011, Page(s): 1
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  • [Copyright notice]

    Publication Year: 2011, Page(s): ii
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  • Table of contents

    Publication Year: 2011, Page(s):iii - x
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  • Welcome message

    Publication Year: 2011, Page(s): 1
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  • Steering committee and subcommittees

    Publication Year: 2011, Page(s):2 - 3
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  • ITC 2010 paper awards

    Publication Year: 2011, Page(s): 4
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  • ITC 2011 most significant paper award

    Publication Year: 2011, Page(s): 5
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  • Technical Program Committee

    Publication Year: 2011, Page(s):6 - 9
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  • ITC technical paper evaluation and selection process

    Publication Year: 2011, Page(s): 10
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  • ITC 2012 call for papers

    Publication Year: 2011, Page(s): 11
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  • Power, programmability, and granularity: The challenges of ExaScale computing

    Publication Year: 2011, Page(s): 12
    Cited by:  Papers (2)
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  • A systems perspective on the R&D of industrial technology

    Publication Year: 2011, Page(s): 13
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  • Invited address

    Publication Year: 2011, Page(s): 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (38 KB) | HTML iconHTML

    Provides an abstract of the invited presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • TTTC: Test Technology Technical Council

    Publication Year: 2011, Page(s): 15
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  • 2011 technical paper reviewers

    Publication Year: 2011, Page(s):18 - 23
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  • Defect Oriented Testing for analog/mixed-signal devices

    Publication Year: 2011, Page(s):1 - 10
    Cited by:  Papers (18)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (519 KB) | HTML iconHTML

    We present an application of Defect Oriented Testing (DOT) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, and test selection. A major challenge of DOT f... View full abstract»

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  • DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management

    Publication Year: 2011, Page(s):1 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB) | HTML iconHTML

    Mixed signal SOCs with integrated RF and power management modules have some distinct requirements associated with them. They are often used in portable and battery operated consumer applications, which are extremely cost and power sensitive. This translates into a few unique design and test constraints on the amount of DFT logic integrated, the permissible test time, and power-up of individual mod... View full abstract»

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  • Test cost reduction through performance prediction using virtual probe

    Publication Year: 2011, Page(s):1 - 9
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the p... View full abstract»

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  • P-PET: Partial pseudo-exhaustive test for high defect coverage

    Publication Year: 2011, Page(s):1 - 8
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB) | HTML iconHTML

    Pattern generation for embedded testing often consists of a phase generating random patterns and a second phase where deterministic patterns are applied. This paper presents a method which optimizes the first phase significantly and increases the defect coverage, while reducing the number of deterministic patterns required in the second phase. The method is based on the concept of pseudo-exhaustiv... View full abstract»

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  • Faster-than-at-speed test for increased test quality and in-field reliability

    Publication Year: 2011, Page(s):1 - 9
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (350 KB) | HTML iconHTML

    Faster-than-at-speed testing is an effective approach to screen small delay defects (SDDs) and increase test quality and in-field reliability. This paper presents a novel framework of faster-than-at-speed test to minimize the slack of the sensitized path for each fault. The basic strategy is to use multiple faster-than-at-speed test timings with endpoint masking for each pattern. By performing a d... View full abstract»

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  • Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing

    Publication Year: 2011, Page(s):1 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (877 KB) | HTML iconHTML

    Capture power management has become a necessity to avoid at-speed scan testing yield loss, especially for modern complex and low power designs. This paper proposes a test pattern generation methodology that utilizes the available clock-gating mechanism, a popular low power design technique, to reduce the launch cycle weighted switching activity (WSA) for at-speed scan testing. Compared to previous... View full abstract»

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  • Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current

    Publication Year: 2011, Page(s):1 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1688 KB) | HTML iconHTML

    With advancing technology nodes, the feature sizes of transistors are scaled down aggressively and the effects of process variations on semiconductor device parameters are becoming worse. Accurate device level statistical models are necessary to understand the composite effect of process variations on IC performance. Statistical models require a large amount of data from measurements made on wafer... View full abstract»

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  • Development of an ATE test cell for at-speed characterization and production testing

    Publication Year: 2011, Page(s):1 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1615 KB) | HTML iconHTML

    This paper describes the development of a test cell intended for thorough characterization and production testing of a complex multigigabit IC. The objective of this project was to provide a straightforward way to transition from characterization testing to the early production ramp with minimal effort while at the same time not restricting or limiting thorough characterization of the IC. This inc... View full abstract»

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  • Actual implementation of multi domain test: Further reduction of cost of test

    Publication Year: 2011, Page(s):1 - 8
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB) | HTML iconHTML

    Multi-Sites Test is the popular way to reduce the cost-of-test (COT) at the wafer and the final test. Limitations exist, however, such as the low Multi-Site Efficiency of analog mixed signal tests and the high system price for large pin count devices. Concurrent Test has been implemented to reduce the test time. This test strategy is difficult to implement without the DFT design of the device. The... View full abstract»

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  • Online timing variation tolerance for digital integrated circuits

    Publication Year: 2011, Page(s):1 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (547 KB) | HTML iconHTML

    Ensuring safe timing increasingly becomes a paramount challenge with the technology scaling to nanoscale. This study aims to provide timing variation detection and tolerance solutions. We first propose a versatile online timing variation detection scheme which can handle multiple types of faults. With the capability of detection, we further propose two tolerance schemes to eliminate runtime margin... View full abstract»

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