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Proceedings Ninth Great Lakes Symposium on VLSI

4-6 March 1999

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Displaying Results 1 - 25 of 105
  • Proceedings Ninth Great Lakes Symposium on VLSI

    Publication Year: 1999
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    Freely Available from IEEE
  • Why is time-varying control necessary for signal processing with locally-connected quantum-dot arrays?

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5 KB)

    Summary form only given, as follows. New nanodevices which encode information into the geometrical charge distribution of artificial (or natural) molecules have been proposed. Functional units are composed by exploiting the electrostatic coupling between neighboring devices. In these units, processing takes place by reshaping the electron density of the molecules, and not by switching electron cur... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):397 - 400
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    Freely Available from IEEE
  • Regression-based macromodeling for delay estimation of behavioral components

    Publication Year: 1999, Page(s):188 - 191
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    This paper presents a methodology for delay estimation of hardware components described at the behavioral-level. The basis of the proposed technique is a well-known theoretical result that relates the entropy of a logic function to the delay of a multi-level implementation of the same function. We propose an improved model for delay estimation, and we prove its validity by means of experiments per... View full abstract»

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  • ALPS: a peak power estimation tool for sequential circuits

    Publication Year: 1999, Page(s):350 - 353
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    Tools for evaluating the worst-case peak power consumption of sequential circuits are highly useful to designers of low-power circuits. Previously proposed methods search for the initial state and the couple of vectors with maximum consumption, without fully considering the reachability of the initial state. This paper shows that this approach can lead to a significant underestimation of the maxim... View full abstract»

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  • Design recovery for incomplete combinational logic

    Publication Year: 1999, Page(s):184 - 187
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Motivated by the problem of reengineering legacy digital circuits for which design information is missing or incomplete, this paper presents a new technique for representing the relationships among the internal components of a combinational circuit. This technique proves to be a powerful tool for redesign, capable of representing internal Boolean relationships in a fully or partially specified mul... View full abstract»

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  • On path delay fault testing of multiplexer-based shifters

    Publication Year: 1999, Page(s):20 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected paths to be robustly testable by 20*log2n+2 test-vector pairs, where n is the length of the shifter. The propagation delay along all other paths is a function of the delay... View full abstract»

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  • A memory design in QCAs using the SQUARES formalism

    Publication Year: 1999, Page(s):166 - 169
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    We present a formalism for implementing circuits with quantum-dot cellular automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism simplifies circuit design from an engineering perspective and overcomes an observed sensitivity of QCA systems to input delays. A design for an addressable shift register is implemented, and promises considerable density g... View full abstract»

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  • A correlation matrix method of clock partitioning for sequential circuit testability

    Publication Year: 1999, Page(s):300 - 303
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    We propose a method of partitioning the set of all flip-flops in a circuit for multiple clock testing. In the multiple clock testing, flip-flops are partitioned into different groups and each group of flip-flops has an independent clock control. In our method, we use a test generator assuming an independent clock control for each flip-flop. We than determine correlation between clock activity for ... View full abstract»

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  • A multilevel cache memory architecture for nanoelectronics

    Publication Year: 1999, Page(s):346 - 347
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (20 KB)

    In this paper, the author presents a new multilevel cache memory architecture which uses only near-neighbour connections, thus eliminating long tracks and rendering the system suitable for nanoelectronic implementation. Operation of the memory is such that the most-recently accessed data is kept closest to the read-write port View full abstract»

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  • PASTA: partial scan to enhance test compaction

    Publication Year: 1999, Page(s):4 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (28 KB)

    We propose a procedure to select flip-flops for partial scan targeting the reduction of test length. We show that significant reductions in test length can be achieved by this procedure. In addition, experimental results show that using heuristics that target the test length does not have to increase the numbers of flip-flops that need to be scanned in order to achieve a given level of fault cover... View full abstract»

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  • An approach for testing safety-critical software

    Publication Year: 1999, Page(s):180 - 183
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    A novel approach for testing the effectiveness, efficiency, safety and relative appropriateness of Computer Interlocking Software (CIS)-a kind of safety-critical software is presented with a software platform developed to support this approach. A brief description of the proposed approach is also included View full abstract»

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  • Functional ATPG for delay faults

    Publication Year: 1999, Page(s):16 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    This paper presents a functional level ATPG tool for delay faults which handles all existing fault models. The tool generates patterns using either binary decision diagrams or Boolean satisfiability. Experimental results are presented on the ISCAS'85 benchmarks View full abstract»

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  • Inductance effects in RLC trees

    Publication Year: 1999, Page(s):56 - 59
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    A closed form solution for characterizing voltage-based signals in an RLC tree is presented. This closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective damping factor of the signal at a specific node in an RLC tree is shown to be a useful figure of merit, As the effective damping factor of a signal increas... View full abstract»

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  • Integration of InAs/AlSb/GaSb resonant interband tunneling diodes with heterostructure field-effect transistors for ultra high-speed digital circuit applications

    Publication Year: 1999, Page(s):162 - 165
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Resonant tunnelling diode based logic circuits offer significant advantages for low power, ultra-high-speed applications. In this work, a low-power resonant interband tunneling diode (RITD)-based logic technology capable of operating at clock rates of at least 12 GHz is reported. The circuits are fabricated using InAs/AlSb/GaSb RITDs. Fanout of at least two at a clock rate of 10 GHz is also report... View full abstract»

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  • A low power charge-recycling CMOS clock buffer

    Publication Year: 1999, Page(s):238 - 239
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    A low power CMOS clock buffer based on charge recycling technique is presented. To accomplish the charge recycling process and avoid introducing the extra short circuit current during the recycling phase, an extra switching circuit and control signal are utilized to keep inverters momentarily tri-state. The feasibility of this design and its improved power efficiency are demonstrated by simulation... View full abstract»

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  • Parallel saturating fractional arithmetic units

    Publication Year: 1999, Page(s):214 - 217
    Cited by:  Papers (5)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    This paper describes the designs of a saturating adder multiplier single MAC unit, and dual MAC unit with single cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation ... View full abstract»

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  • Memory organization of a single-chip video signal processing system with embedded DRAM

    Publication Year: 1999, Page(s):42 - 45
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element View full abstract»

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  • Monolithic microprocessor and RF transceiver in 0.25-micron FDSOI CMOS

    Publication Year: 1999, Page(s):332 - 333
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    A monolithic RFIC in 0.25-micron fully-depleted SOI CMOS has been designed consisting of a microcoded 8-bit 33-MHz microprocessor, a 400-MHz 8-bit ASK-modulated RF transceiver and two integrated dc-dc voltage converters for power management. This architecture exploits a low-power (sub 2-V) digital process for mixed-signal VLSI in a die size measuring 2.2 mm×2.2 mm View full abstract»

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  • Hierarchical scheduling in high level synthesis using resource sharing across nested loops

    Publication Year: 1999, Page(s):140 - 143
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    This paper presents a resource-constrained scheduling algorithm for hierarchical behavioral specifications containing nested loops. The algorithm attempts to share resources across levels, to schedule operations that belong to different levels of the nested loop structures in the specifications as well as operations that belong to the same level. We compare the results of scheduling using our algo... View full abstract»

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  • On optimizing test strategies for analog cells

    Publication Year: 1999, Page(s):92 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    The purpose of this paper is to analyze an optimization method to improve the testability of structural defects, such as bridges and opens, in low-power low-voltage analog circuits. The approach consists of finding an optimum subset of tests which maximizes the fault coverage with minimum cost. An application example is given to illustrate the proposal by studying the fault coverage obtained using... View full abstract»

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  • A software acceptance testing technique based on knowledge accumulation

    Publication Year: 1999, Page(s):296 - 299
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    System acceptance testing in general relies on the specification of system requirements, but for a complex system, especially for complex safety systems, the issue of whether system requirements specified by users are complete should be considered. This paper presents a software acceptance testing technique based on knowledge accumulation, which will help to expose the software faults caused by th... View full abstract»

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  • Resonant tunneling transistors for threshold logic circuit applications

    Publication Year: 1999, Page(s):344 - 345
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Resonant tunneling transistors (RTTs) and linear threshold gates based on monostable-bistable logic transition elements (MOBILEs) are promising candidates for nano-scale integrated circuits. In this paper the design methodology of RTT logic gates is discussed and experimental results of a monolithically integrated NAND-NOR gate are presented. To exploit the computational functionality of threshold... View full abstract»

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  • A VLSI architecture for ATM algorithm-agile encryption

    Publication Year: 1999, Page(s):325 - 328
    Cited by:  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    In this paper a VLSI architecture is proposed for an algorithm-agile encryptor for ATM networks. The architecture is based on a circular sorting queue that buffers and switches incoming cells to the appropriate encryption pipelines. It also handles multicast cells that require different encryption algorithms for different destinations. Delay and loss priority are analyzed for multi-class traffic p... View full abstract»

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  • SINMEF-a decomposition based synthesis tool for large FSMs

    Publication Year: 1999, Page(s):176 - 179
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    This paper describes the SINMEF environment, composed of the DECMEF and the SIS systems, used to synthesize large finite state machines (FSMs). The DECMEF system consists of a set of tools to decompose a FSM into a set of cooperating sub-FSMs. An efficient cost function is used to guide the decomposition process. The decomposed FSMs are state encoded and further optimized and technology mapped usi... View full abstract»

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