Proceedings Ninth Great Lakes Symposium on VLSI

4-6 March 1999

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  • Proceedings Ninth Great Lakes Symposium on VLSI

    Publication Year: 1999
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    Freely Available from IEEE
  • Why is time-varying control necessary for signal processing with locally-connected quantum-dot arrays?

    Publication Year: 1999
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    Summary form only given, as follows. New nanodevices which encode information into the geometrical charge distribution of artificial (or natural) molecules have been proposed. Functional units are composed by exploiting the electrostatic coupling between neighboring devices. In these units, processing takes place by reshaping the electron density of the molecules, and not by switching electron cur... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):397 - 400
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    Freely Available from IEEE
  • Hierarchical scheduling in high level synthesis using resource sharing across nested loops

    Publication Year: 1999, Page(s):140 - 143
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (240 KB)

    This paper presents a resource-constrained scheduling algorithm for hierarchical behavioral specifications containing nested loops. The algorithm attempts to share resources across levels, to schedule operations that belong to different levels of the nested loop structures in the specifications as well as operations that belong to the same level. We compare the results of scheduling using our algo... View full abstract»

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  • A fully pipelined, 700 MBytes/s DES encryption core

    Publication Year: 1999, Page(s):386 - 387
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (32 KB)

    Fully-pipelined, 56-bit DES de/encryption and authentication at memory-bus bandwidths is now feasible. We describe a custom, 7 square mm, 120 mW core in 4-metal 0.35 μm CMOS. Performance allows on-the-fly encryption of 64-bit, 66 MHz PCI traffic, and hence typical network traffic. FPGA, synthesized, and 3-metal versions are compared View full abstract»

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  • Blending symbolic matrix and dimensional numerical simulation methodology for mechatronics systems

    Publication Year: 1999, Page(s):270 - 273
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (64 KB)

    The methodology for the integration of design domains towards the purpose of controlling dynamic mechatronics systems is the current challenge of the modern engineer. Scaling issues for both the mechanical and electrical parameters are critical to the successful design and implementation of a mechatronic system. In approaching the scaling design methodology for future submicron fabrication, new di... View full abstract»

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  • Memory organization of a single-chip video signal processing system with embedded DRAM

    Publication Year: 1999, Page(s):42 - 45
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (184 KB)

    A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element View full abstract»

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  • Self-checking of FPGA-based control units

    Publication Year: 1999, Page(s):292 - 295
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (324 KB)

    The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions. A self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. Comparison of code vectors being transferred between the blocks of... View full abstract»

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  • An integrated approach for synthesizing LUT networks

    Publication Year: 1999, Page(s):136 - 139
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    This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many decomposition methods that are not only algebraic but also functional are integrated. Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The experimental r... View full abstract»

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  • Memory chip BIST architecture

    Publication Year: 1999, Page(s):384 - 385
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (112 KB)

    This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is “free” for some faults during test. 4. Is never subject to aliasing. 5. Depending upon the test length, it can... View full abstract»

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  • Design automation of MEMS systems using behavioral modeling

    Publication Year: 1999, Page(s):266 - 269
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (172 KB)

    We propose a behavioral approach to designing MEMS devices. This approach differs from much current research in that this approach would not require dimensional parameters for the device, but instead would require a high level, functional or behavioral description. This paper examines how such an approach would work using a case study of an optical processor manually designed using the MUMP's proc... View full abstract»

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  • Efficient and safe asynchronous wave-pipeline architectures for datapath and control unit applications

    Publication Year: 1999, Page(s):38 - 41
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    This paper presents a generalization of a previously proposed asynchronous wave-pipeline architecture. Four-phase and two-phase communication units supporting more than one wave in the logic are proposed. General feedback structures are then outlined. Simulations from a 16-bit add-and-shift ring demonstrate their feasibility. The same architecture is applicable for both datapath and control enabli... View full abstract»

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  • Symbolic multi-level verification of refinement

    Publication Year: 1999, Page(s):288 - 291
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (324 KB)

    VLSI-system design can, in general, be characterized in terms of the step-wise refinement of intermediate solutions. Despite the fact that such refinements usually do not preserve time-scales, current formal verification approaches mostly start from the assumption that both specification and implementation utilize the same scales of time. Realizing the importance of being able to cope with differe... View full abstract»

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  • Reducing BDD size by exploiting structural connectivity

    Publication Year: 1999, Page(s):132 - 135
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (84 KB)

    Computer-aided design tools have been limited by the use of the Binary Decision Diagram (BDD). The major drawback of the BDD is its abundant usage of CPU time and memory. Techniques such as BDD variable ordering and sharing have been used in the past to address the size issue. However these techniques remain to be limited to modest-sized circuits. In this paper, we present a significant variation ... View full abstract»

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  • PASTA: partial scan to enhance test compaction

    Publication Year: 1999, Page(s):4 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (28 KB)

    We propose a procedure to select flip-flops for partial scan targeting the reduction of test length. We show that significant reductions in test length can be achieved by this procedure. In addition, experimental results show that using heuristics that target the test length does not have to increase the numbers of flip-flops that need to be scanned in order to achieve a given level of fault cover... View full abstract»

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  • A novel low power energy recovery full adder cell

    Publication Year: 1999, Page(s):380 - 383
    Cited by:  Papers (64)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (632 KB)

    A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low powerful adders; the transmission function adder (TFA) the dual value logic (DVL) adder and the fourteen transistor (14 T) full adder. The proposed SERF adder design was proven to be s... View full abstract»

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  • Memory unit design for real time DSP applications

    Publication Year: 1999, Page(s):260 - 263
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (176 KB)

    Today, the design complexity for new applications (such as telecommunication, multi media, internet), requires new high level tools which enable us to translate the behavioral description into hardware. All of the recent High Level Synthesis tools are able to transform high level specifications in an ASIC based on processing and control units. In general, these tools do not handle a real optimizat... View full abstract»

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  • The design of a register renaming unit

    Publication Year: 1999, Page(s):34 - 37
    Cited by:  Papers (5)
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    Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations View full abstract»

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  • Fault coverage estimation for early stage of VLSI design

    Publication Year: 1999, Page(s):105 - 108
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (224 KB)

    This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, α. The fault coverages using three different testing scenarios, which ar... View full abstract»

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  • A hierarchical approach to the formal verification of embedded systems using MDGs [microcontrollers]

    Publication Year: 1999, Page(s):284 - 287
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (28 KB)

    With the increasing emergence of mixed hardware/software systems, it is important to ensure the correctness of such a system formally, particularly for real-time and safety critical applications. We present a hierarchical approach to modeling and formally verifying an embedded system at higher levels of abstraction, using Multiway Decision Graphs (MDGs). We demonstrate our approach on the embedded... View full abstract»

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  • Inductance effects in RLC trees

    Publication Year: 1999, Page(s):56 - 59
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (112 KB)

    A closed form solution for characterizing voltage-based signals in an RLC tree is presented. This closed form solution is used to derive figures of merit to characterize the effects of inductance at a specific node in an RLC tree. The effective damping factor of the signal at a specific node in an RLC tree is shown to be a useful figure of merit, As the effective damping factor of a signal increas... View full abstract»

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  • Logic in wire: using quantum dots to implement a microprocessor

    Publication Year: 1999, Page(s):118 - 121
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB)

    Despite the seemingly endless upwards spiral of modern VLSI technology many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to look at alternative technologies, one of which is based on quantum dots, called quantum cellular automata. While the first such devices have been fabricated, little is known about how to design complete systems. This paper su... View full abstract»

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  • Efficient algorithms for finding highly acceptable designs based on module-utility selections

    Publication Year: 1999, Page(s):128 - 131
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    In this paper we present an iterative framework to solve module selection problem under resource, latency, and power constraints. The framework associates a utility measure with each module. This measurement reflects the usefulness of the module for a given a design goal. Using modules with high utility values will result in superior designs. We propose a heuristic which iteratively perturbs modul... View full abstract»

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  • Residue arithmetic circuits based on signed-digit number representation and the VHDL implementation

    Publication Year: 1999, Page(s):218 - 221
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (212 KB)

    Residue arithmetic circuits based on radix-2 signed-digit (SD) number representation, using integers 2p and 2p±1 as moduli of residue number system (RNS), are presented. The modulo m addition, m=2p or m=2p±1, is performed by a carry-free SD adder and the module m multiplier is constructed using a binary modulo m SD adder tree. The implement... View full abstract»

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  • An approach for testing safety-critical software

    Publication Year: 1999, Page(s):180 - 183
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    A novel approach for testing the effectiveness, efficiency, safety and relative appropriateness of Computer Interlocking Software (CIS)-a kind of safety-critical software is presented with a software platform developed to support this approach. A brief description of the proposed approach is also included View full abstract»

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