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Electronic System Design (ISED), 2011 International Symposium on

Date 19-21 Dec. 2011

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Displaying Results 1 - 25 of 76
  • [Front cover]

    Publication Year: 2011, Page(s): C1
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  • [Title page i]

    Publication Year: 2011, Page(s): i
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  • [Title page iii]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - x
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  • Message from General Chairs

    Publication Year: 2011, Page(s): xi
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  • Message from Technical Program Chairs

    Publication Year: 2011, Page(s): xii
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  • Organizing Committee

    Publication Year: 2011, Page(s): xiii
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  • Technical Program Committee

    Publication Year: 2011, Page(s):xiv - xvi
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  • Steering Committee

    Publication Year: 2011, Page(s): xvii
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  • Additional Reviewers

    Publication Year: 2011, Page(s): xviii
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  • Invited Plenary Talks

    Publication Year: 2011, Page(s):xix - xxxi
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  • Concurrent Dual Band Transmitter for 2.4/5.2GHz Wireless LAN Applications

    Publication Year: 2011, Page(s):1 - 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1195 KB) | HTML iconHTML

    The paper reports design of a concurrent dual band transmitter for simultaneous operation at 2.4/5.2GHz. A combination of direct conversion and parallel architectures is utilized to satisfy the requirements of various signal modulation schemes that are employed in wireless local area network. The entire transmitter architecture is implemented using hybrid microwave integrated circuit (HMIC) techno... View full abstract»

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  • Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL

    Publication Year: 2011, Page(s):6 - 11
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    The design and optimization complexity of analog/mixed-signal (AMS) components causes significant increase in the design cycle as the technology progresses towards deep nanoscale. This paper presents a two-tier approach to significantly reduce the design cycle time by combining accurate metamodeling and intelligent optimization. The paper first presents metamodeling which is a surrogate model of a... View full abstract»

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  • Performance Study of Harmony Search Algorithm for Analog Circuit Sizing

    Publication Year: 2011, Page(s):12 - 17
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (271 KB) | HTML iconHTML

    Automation in nominal design of analog circuits considerably reduces the overall time to market of mixed-mode ICs. Application of meta-heuristic optimization algorithms with simulator level fitness evaluation for circuit sizing is a popular automation approach. In this work, with the same approach, we investigate the performance of Harmony Search (HS) algorithm. HS is a relatively new meta-heurist... View full abstract»

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  • A Harmonically Superior Switching Modulator with Wide Baseband and Real-Time Tunability

    Publication Year: 2011, Page(s):18 - 23
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2071 KB) | HTML iconHTML

    The paper proposes a class of switching modulators with reduced harmonics to allow a wide base band. In an ordinary switching modulator, the harmonics are rich and the operating bandwidth is rather limited. Here we are advancing a harmonic elimination technique to place the unwanted harmonics at a frequency farther away from the fundamental. It is a novel PWM method where a reference sinusoid with... View full abstract»

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  • A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter

    Publication Year: 2011, Page(s):24 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (311 KB) | HTML iconHTML

    In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over ... View full abstract»

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  • Nonlinear Inductance Measurement Using an Energy Storage Approach

    Publication Year: 2011, Page(s):30 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    A novel method to measure inductance of power inductors is presented in this paper. Energy stored in inductors was used to measure the nonlinear inductance as function of current flow. Inductance was measured for air core (control sample) and ferrite core inductors with increasing levels of currents through them. It was found that air core inductor behaved linearly as expected. Data for ferrite co... View full abstract»

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  • Highly Sensitive ?R/R Measurement System for Nano-electro-Mechanical Cantilever Based Bio-sensors

    Publication Year: 2011, Page(s):34 - 38
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (338 KB) | HTML iconHTML

    Functionalized piezoresistive nano-electromechanical cantilevers are promising tools for sensor applications. This paper reports an integration of custom fabricated piezoresistive cantilever sensors and sensitive analog front end circuit for detection of bio-markers. The system operates on the principles of nano-meter deflection of cantilever sensors, due to antigen-antibody interactions, which in... View full abstract»

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  • PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression

    Publication Year: 2011, Page(s):39 - 44
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    Low power consumption, stability, and PVT-tolerance in Static Random Access Memories (SRAM) is essential for nanoscale System-on-Chip (SoC) designs. In this paper, a novel design flow is presented for optimizing a figure of merit called Power to Static-Noise-Margin (SNM) Ratio (PSR). The minimization of PSR results in power minimization and SNM maximization of nano-CMOS SRAM circuits which are mut... View full abstract»

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  • A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support

    Publication Year: 2011, Page(s):45 - 50
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (679 KB) | HTML iconHTML

    The rapid evolution of reconfigurable computing places a great demand for Floating Point Multipliers (FPMs) capable of supporting wide range of application domains from scientific computing to multimedia applications. While former needs the support of higher precision formats like Double Precision(DP) / Extended Precision(EP), the latter needs Single Instruction Multiple Data (SIMD) feature in Sin... View full abstract»

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  • A New Look-Up Table Approach for High-Speed Finite Field Multiplication

    Publication Year: 2011, Page(s):51 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB) | HTML iconHTML

    This paper presents a new high-speed multiplier over GF(2m) based on look-up table (LUT) approach. A straight-forward LUT-based multiplication requires a table of size (m x 2m) bits for the Galois field of order m which is quite large for the fields of large orders recommended by the National Institute of Standards and Technology (NIST). Therefore, in this paper, we propose a... View full abstract»

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  • VLSI Implementation of Wavelet Based Robust Image Watermarking Chip

    Publication Year: 2011, Page(s):56 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1533 KB) | HTML iconHTML

    Progress in the digital multimedia technologies during last decade has offered many facilities in the transmission, reproduction and manipulation of data. However, this advance has also brought the problem such as copyright protection for content providers. Digital watermarking is proposed solution for copy right protection for multimedia. The goal of hardware assisted watermarking is to achieve l... View full abstract»

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  • Design of Low Power, High Performance FIR Filter Using Modified Differential Evolution Algorithm

    Publication Year: 2011, Page(s):62 - 66
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (182 KB) | HTML iconHTML

    In digital filters, maximum power consumption occurs during multiplication operations. Hence, to reduce power consumption, the number of multiplications has to be minimized. The number of Signed-Power-of-Two (SPT) terms in the filter coefficients has to be optimally minimized, without compromising on the filter response. A modified Differential Evolution (MDE) algorithm has been used to generate o... View full abstract»

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  • Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications

    Publication Year: 2011, Page(s):67 - 71
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (447 KB) | HTML iconHTML

    Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique computational technique for calculations based on 16 Sutras (Formulae). Novel divider architecture for high speed VLSI application using such ancient methodology is presented in this paper. Propagation delay and dynamic power consumption of a divider circuitry were minimized significantly by removing unnecessary ... View full abstract»

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