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Test Symposium (ATS), 2011 20th Asian

Date 20-23 Nov. 2011

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Displaying Results 1 - 25 of 105
  • [Front cover]

    Publication Year: 2011 , Page(s): C1
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  • [Title page i]

    Publication Year: 2011 , Page(s): i
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  • [Title page iii]

    Publication Year: 2011 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011 , Page(s): iv
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  • Table of contents

    Publication Year: 2011 , Page(s): v - xiii
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  • Message from General Co-chairs

    Publication Year: 2011 , Page(s): xiv
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  • Message from Technical Program Co-chairs

    Publication Year: 2011 , Page(s): xv
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  • Organizing Committee

    Publication Year: 2011 , Page(s): xvi
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  • Program Committee

    Publication Year: 2011 , Page(s): xvii - xviii
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  • Steering Committee

    Publication Year: 2011 , Page(s): xix
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  • Reviewers

    Publication Year: 2011 , Page(s): xx
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  • On Detecting Transition Faults in the Presence of Clock Delay Faults

    Publication Year: 2011 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods. View full abstract»

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  • Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip

    Publication Year: 2011 , Page(s): 7 - 14
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    Manufacturing test for clock-domain crossing(CDC) defects is a major challenge for multi-core system-on chip(SoC) designs in the nanometer regime. Setup- and hold time violations in flip-flops situated on clock boundaries may lead to catastrophic failures, even when circuits are equipped with synchronizers at clock boundaries. In this work, we comprehensively study the effect of CDC faults, and propose a number of fault models to target such defects. In addition, we develop an automatic test-pattern selection method for CDC fault detection. This work is motivated by the fact that CDC faults cannot always be detected by conventional ATPG methods. The results of applying the proposed method to a number of IWLS'05 benchmarks demonstrate the effectiveness of our approach. View full abstract»

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  • On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test

    Publication Year: 2011 , Page(s): 15 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2074 KB) |  | HTML iconHTML  

    Memory interface speed has been rapidly increasing to overcome the performance gaps between microprocessor and memory. Testing the I/O timing parameters at-speed has become a challenge because of the limitations on the test clock frequencies provided by low-cost testers. This paper presents a technique to generate a dual-capture signal with a programmable delay for both rising and falling transitions, which effectively tests double-data rate memory interface timing. The relative delay difference between data and clock paths is measured for the I/O timing test instead of using complicated test vectors. The test clock frequency is programmed in a wide operating range with 20 ps resolution. The proposed on-chip programmable double-capture generator can be also easily integrated with the current scan-based delay test methods. The scheme has low area overhead, low design effort, and is also compatible with low-cost testers. View full abstract»

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  • Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-sampling

    Publication Year: 2011 , Page(s): 21 - 26
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (545 KB) |  | HTML iconHTML  

    High speed signal acquisition and characterization contributes a significant amount to the total test cost of the finished product in modern high speed systems. Incoherent under-sampling allows robust and low cost signal acquisition without requiring a prior accurate knowledge of signal period. In this paper we propose a frequency estimation and signal reconstruction technique for incoherently sub-sampled periodic waveforms that is based on a time domain cost function. The method reduces the per iteration cost by a factor of log N compared to frequency domain cost functions. The proposed method estimates the period of a test signal with much fewer samples without degradation of accuracy. View full abstract»

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  • Temperature Dependent Test Scheduling for Multi-core System-on-Chip

    Publication Year: 2011 , Page(s): 27 - 32
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (535 KB) |  | HTML iconHTML  

    Recent research has shown that some defects are detect resilient under normal or high temperature, therefore tests for those defects must be applied under lower temperature. On the other hand, some tests need to be applied under high temperature to improve the detection sensitivity. Thus temperature dependent testing which applies tests at different temperature ranges is needed. This paper discusses and gives a formulation of the temperature dependent test scheduling problem. In the proposed test scheduling scheme, each test is associated with a lower temperature bound and an upper temperature bound to define the temperature range within which the test must be applied. A list schedule based test scheduling algorithm is proposed to find the earliest starting time of each test. Cooling period is inserted when the core temperature is too high and heating sequence is applied when the core temperature is below the required specified temperature for the core. Simulation studies are performed for ITC'02 SoC benchmarks and test scheduling results are shown. View full abstract»

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  • Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

    Publication Year: 2011 , Page(s): 33 - 39
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (213 KB) |  | HTML iconHTML  

    In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at their different operating voltages, which leads to higher test time and test cost. We propose a fast heuristic test scheduling technique for multicore chips that minimize the testing time when each core is tested at multiple voltage settings as well as if it is tested for state retention when the core switches between two voltage levels. Experimental results for two test-case SOCs from industry highlight the effectiveness of the proposed method. View full abstract»

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  • Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data

    Publication Year: 2011 , Page(s): 40 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    A new test application scheme is proposed for low-power scan testing, which is able to compress test data significantly. A combination of a scan architecture and an existent test compression scheme can compress test data even better. Test power can be reduced greatly based on the new test application scheme, according to which only a subset of scan flip-flops shifts a test vector or captures test responses in any clock cycle. Test response data can be another important problem. A new test response compaction scheme called selective test response collection is proposed to reduce test response data. Selective test response collection combines with a structure-based test response compactor, according to which many test response data can be dropped. Experimental results show that the proposed test application scheme can efficiently reduce test power, compress test stimulus data, and compact test response data while test application cost can be well-controlled. View full abstract»

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  • Low Power Test-Compression for High Test-Quality and Low Test-Data Volume

    Publication Year: 2011 , Page(s): 46 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB) |  | HTML iconHTML  

    Test data decompressors targeting low power scan testing introduce significant amount of correlation in the test data and thus they tend to adversely affect the coverage of unmodeled defects. In addition, low power decompression needs additional control data which increase the overall volume of test data to be encoded and inevitably increase the volume of compressed test data. In this paper we show that both these deficiencies can be efficiently tackled by a novel pseudorandom scheme and a novel encoding method. The proposed scheme can be combined with existing low power decompressors to increase unmodeled defect coverage and almost totally eliminate control data. Extensive experiments using ISCAS and IWLS benchmark circuits show the effectiveness of the proposed method when it is combined with state-of-the-art decompressors. View full abstract»

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  • Multi-cycle Test with Partial Observation on Scan-Based BIST Structure

    Publication Year: 2011 , Page(s): 54 - 59
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (283 KB) |  | HTML iconHTML  

    Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode. The experimental result shows that the partial observation achieves fault coverage improvement with small hardware overhead than the full observation. View full abstract»

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  • SSTKR: Secure and Testable Scan Design through Test Key Randomization

    Publication Year: 2011 , Page(s): 60 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal signals of a chip. However, this property also facilitates hackers to use scan architecture as a means to breach chip security. This paper addresses this issue by proposing a new method called Secure and testable Scan design through Test Key Randomization(SSTKR). SSTKR is a key based method to prevent hackers from stealing secret information. Linear Feedback Shift Register (LFSR) is used to generate authentication keys to be embedded in test vectors. Unique key is used for every test vector which prevents scan based side channel attacks effectively. Any attempt to steal secret information will lead to a randomized response. SSTKR has very low area and test time overhead without performance penalty. Our approach also facilitates in-field test of the chip. View full abstract»

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  • An Innovative Methodology for Scan Chain Insertion and Analysis at RTL

    Publication Year: 2011 , Page(s): 66 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability issues early in the design flow, and leveraging the optimization done by the synthesis tool. But inserting DFT logic such as a full-scantest logic before synthesis brings its own challenges: the earlier it is inserted in the flow, the harder it is to provide low-overhead insertion. In this work, we combine the use of a lightweight synthesis with graph models for inferring logical proximity information from the design, and then use classic approximation algorithms for the traveling salesman problem to determine the scan-stitching ordering. We show how this procedure allows the decrease of the cost of both scan analysis and implementation, by measuring total wire length on placed and routed benchmark designs, both academic and industrial. View full abstract»

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  • Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing

    Publication Year: 2011 , Page(s): 72 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    Test and testability are essential concerns for design in any abstraction level, and are even more challenging for high level designs. Because of complexity of today's designs, design at ESL (electronic system level) using transaction level modeling (TLM) has become a focal point of today's system level designers. However, there are no standard test methods or conventions proposed for this level of abstraction. Built-In Self-Test is a conventional DFT method, well defined in gate level and RT level. In this work by inspiration from the standard RTL BIST architectures, and finding similarities in TLM-2 designs and the RTL designs being tested by standard RTL BISTs, a number of TLM-2 BIST architectures are proposed. The overhead of inserting these BISTs in the original design is calculated. View full abstract»

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  • Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing

    Publication Year: 2011 , Page(s): 78 - 83
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (187 KB) |  | HTML iconHTML  

    Shrinking feature sizes have magnified deep sub-micron effects, resulting in integrated circuits prone to timing-related defects. Stringent test quality requirements have therefore mandated the use of at-speed testing schemes, however, excessive switching activity during the launch operation may result in yield loss. In this paper, we propose a design partitioning technique that can reduce power dissipation during launch and capture operations in the launch-off-shift (LOS) based at-speed testing scheme. As opposed to the existing partitioning techniques, the proposed low-power framework enables the re-use of a (compact and high quality) set of patterns generated by a conventional power-unaware LOS ATPG tool as is, which can be applied in a low power manner. To tackle this challenge, we derive partitioning rules as well as the non-intrusive DfT support needed, enabling the transformation of power-thriftless patterns into power-frugal ones, while retaining pattern count and test quality (fault and ancillary defect coverage) intact. View full abstract»

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  • Low Power Decompressor and PRPG with Constant Value Broadcast

    Publication Year: 2011 , Page(s): 84 - 89
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of existing DFT logic, its use results in a low switching activity during all phases of scan test: loading, capture, and unloading. It reduces power consumption to or below a level of a functional mode, thus helping to resolve problems related to power dissipation, voltage drop, and increased temperature. View full abstract»

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