Date 14-15 Nov. 2011
Filter Results
Displaying Results 1 - 25 of 57
-
[Title page]
|
PDF (142 KB)
-
[Copyright notice]
|
PDF (34 KB)
-
Table of contents
|
PDF (289 KB)
-
-
-
10 GS/s 8-bit bipolar THA in SiGe technology
|
PDF (1046 KB)
-
Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance
|
PDF (1490 KB)
-
A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback
|
PDF (1449 KB)
-
Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs
|
PDF (1068 KB)
-
-
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems
|
PDF (1605 KB)
-
-
-
-
Magnitude scaling for increased SFDR in DDFS
|
PDF (1592 KB)
-
-
-
Modeling of cascode modulated power amplifiers
|
PDF (1069 KB)
-
A low voltage low power CMOS analog multiplier
|
PDF (1393 KB)
-
-
A mixed mode design flow for multi GHz ADPLLs
|
PDF (1472 KB)
-
Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixers
|
PDF (1365 KB)
-
-
Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner
|
PDF (2259 KB)
-
Dynamic bias schemes for class-C VCOs
|
PDF (815 KB)
