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Date 14-15 Nov. 2011

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Displaying Results 1 - 25 of 57
  • [Title page]

    Publication Year: 2011 , Page(s): 1
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    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2011 , Page(s): 1
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 2011 , Page(s): 1 - 7
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    Freely Available from IEEE
  • IR-UWB technology on next generation RFID systems

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (707 KB) |  | HTML iconHTML  

    Radio-frequency identification (RFID) systems are widely used in our daily life. Although several proposed solutions are in production, limitations are still significant. In this paper, the current RFID technology is reviewed and major shortcomings are discussed. Our expected features on next generation RFID systems are described. Finally, we propose an impulse-radio (IR) ultra-wideband (UWB) RFID system and present how to improve the performance by using IR-UWB technology. View full abstract»

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  • Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1505 KB) |  | HTML iconHTML  

    Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology. View full abstract»

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  • 10 GS/s 8-bit bipolar THA in SiGe technology

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1046 KB) |  | HTML iconHTML  

    Design and measurement of the bipolar Track-and-Hold Amplifier is described in this paper. The circuit works at the sample rate of 10 GS/s and has linearity of 8-bit at input signal of 3 GHz. Based on the open-loop switched emitter follower architecture, the circuit implies several techniques to achieve 8-bit performance at GHz range. An input buffer and switch were modified to decrease errors and increase the speed. View full abstract»

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  • Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1490 KB) |  | HTML iconHTML  

    A low power 10-bit successive approximation A/D converter which is designed for implantable bioelectronics is presented. The converter has a charge scaling digital-to-analog converter which also samples the input signal. The charge scaling capacitance is in a split-capacitor configuration that has a total input capacitance which is 95.5 % smaller compared to a conventional design and 25%smaller compared to a conventional split-capacitor design. The converter operates at 308 kS/s and has a single-ended structure. The circuit is simulated with a 0.35 μm 4M2P CMOS process. Simulation results for the proposed A/D converter are presented. View full abstract»

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  • A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1449 KB) |  | HTML iconHTML  

    This paper presents a low-power multi-bit continuous-time ΔΣ modulator with a new approach to clock jitter reduction utilizing switched-capacitor-resistor techniques. The modulator features a 3rd order loop filter, implemented with active RC integrators, and 3-bit quantizer and feedback DACs. The ΔΣ modulator has been implemented in a 65nm CMOS process and tested. It achieves a peak SNDR of 70 dB in a 125 kHz signal bandwidth while consuming 380 μW. The combination of a high-order loop filter and multi-bit quantizer allows for a high resolution at a low sampling frequency of 4MHz, corresponding to an oversampling ratio of 16. View full abstract»

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  • Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB) |  | HTML iconHTML  

    The complexity of narrow transition band FIR filters is high and can be reduced by using frequency response masking (FRM) techniques. These techniques use a combination of periodic model filters and masking filters. In this paper, we show that time-multiplexed FRM filters achieve lower complexity, not only in terms of multipliers, but also logic elements compared to time-multiplexed single stage filters. The reduced complexity also leads to a lower power consumption. Furthermore, we show that the optimal period of the model filter is dependent on the time-multiplexing factor. View full abstract»

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  • On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (774 KB) |  | HTML iconHTML  

    This paper treats the hardware architecture and implementation of mixed radix FFTs with cores of radix 3 and radix 5 in addition to the standard radix 2 core. The implementation flow graphs of the higher radix cores are presented together with a description of how these cores affect a pipelined FFT implementation. It is shown that the mixed radix FFT is more expensive than the radix 2 implementation - a mixed radix FFT of 1200 points require 36 real multipliers in a pipelined implementation whereas a 2048 radix 2 FFT needs 30 real multipliers. However, half of the multipliers in the mixed radix case can be constant. Therefore it is still feasible to use the mixed radix FFT if an algorithm calls for it. View full abstract»

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  • Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1605 KB) |  | HTML iconHTML  

    This paper has evaluated the overhead requirements for IOTA pulse shaping filters employed in faster-than-Nyquist multicarrier systems. Faster-than-Nyquist signaling has shown the promise of improving bandwidth efficiency, but comes at the cost of increased processing complexity in the transceiver. The IOTA filter being one of the blocks contributing for the processing overhead, different architectural options have been evaluated. A comparison is drawn between the architectures of the IOTA filter and the suitable architecture with moderate hardware overhead is chosen for implementation. View full abstract»

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  • On wafer X-parameter based modeling of a switching cascode power amplifier

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1722 KB) |  | HTML iconHTML  

    X-parameters have been introduced as the natural extension of S-parameters capable of characterizing a nonlinear device excited by a large-signal input. This paper describes validation of the X-parameter model of a switching cascode power amplifier (PA), which has strong nonlinearity. The X-parameter model of the PA was measured and extracted by an Agilent N5245A PNA-X. Measurements were done on wafer and deem-bedded to the input and output pads of the device. An Enhanced Data rates for GSM Evolution (EDGE) signal was applied to the model for simulations. The simulated relative levels of output spectrum and RMS value of error vector magnitude (EVM) were compared with the measured data in order to validate the X-parameter model. A good match was achieved between the simulation and measurement. The maximum difference between the simulated and measured relative levels of output spectrum is 4 dB. The maximum error between the simulated and measured EVM is less than 3 %-point. View full abstract»

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  • Wideband limit study of a GaN power amplifier using two-tone measurements

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1634 KB) |  | HTML iconHTML  

    This paper studies the wideband limit (WBL) of a GaN RF power amplifier (PA). The WBL study is achieved by a PA characterization using two-tone measurements. The characterization method allows to identify the dependency of PA memory effects on the two-tone frequency spacing. PA memory effects (MEs) are measured using the opening in the AM/AM and AM/PM curves and they were found to be located in a limited range of tone spacings. The outcome of this characterization procedure is the identification of the PA wideband limit defined as the upper limit of the MEs frequency range. The most interesting phenomenon related to the WBL is that for all tone spacings beyond the WBL the AM/AM curves of the PA collapse to a quasi-static case, which is different from the static case. The presence of the wideband limit is not so evident from AM/PM curves, where the phase loop is not collapsing beyond WBL. The wideband limit is an important aspect of the DUT behaviour and can be used to improve the accuracy of the DUT behavioral model identifying its memory range. View full abstract»

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  • A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1052 KB) |  | HTML iconHTML  

    In this paper, a ternary Full-Adder capable of reducing four input trits (ternary-digits) to two output trits is presented using the novel Ternary Adiabatic Logic (TAL) family. As well as presenting TAL, a possible design methodology for TAL circuits using Ordered Ternary Decision Diagrams (OTDDs) is presented, and the potential of higher-radix adiabatic logic families is discussed. Under typical process conditions on a 0.35μm process, front-end only simulations of the TAL Full-Adder using an ideal-ramp power-clock waveform show it to consume an average of 216fW per addition when operated at 1MHz. View full abstract»

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  • Magnitude scaling for increased SFDR in DDFS

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1592 KB) |  | HTML iconHTML  

    When generating a sine table to be used in, e.g., frequency synthesis circuits, a widely used way to assign the table content is to simply take a sine wave with the desired amplitude and quantize it using rounding. This results in uncontrolled rounding of up to 0.5 LSB, causing some noise. In this paper we present a method for increasing the signal quality, simply by adjust the amplitude within a ±0.5 range from the intended. This will not affect the maximum value of the sinusoid, but can increase the spurious free dynamic range with some dB. View full abstract»

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  • A 2.7–6.1GHz CMOS local oscillator based on frequency multiplication by 3/2

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1160 KB) |  | HTML iconHTML  

    Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1GHz with a performance suitable for cellular standards. It shows a noise floor below -150 dBc and a spurious level below -35 dBc. The multiplier by 3/2 consumes 5mA and the VCO draws 10mA from a 1.2V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this solution, compared to the use of multiple LC VCOs. View full abstract»

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  • Very high bandwidth semi-digital PLL with large operating frequency range

    Publication Year: 2011 , Page(s): 1 - 6
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2112 KB) |  | HTML iconHTML  

    A new method of designing a very high bandwidth semi-digital PLL with a large operating frequency range from 100MHz to 1GHz is proposed. The PLL is modelled in Z-domain. The simulation results is also matched with the modelling to ensure that the PLL is stable for very high bandwidth. The bandwidth achieved is (1/4)th of the input reference frequency for the whole operating range mentioned. View full abstract»

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  • Modeling of cascode modulated power amplifiers

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1069 KB) |  | HTML iconHTML  

    Two models of the cascode modulated polar power amplifier (PA) are presented. The cascode modulated PA, that operates as a switch mode amplifier with class-E like output network, has a highly nonlinear transfer characteristic. The proposed empirical model is based on modeling of the peak drain current through the cascode connected transistors. A simplified analytical model, that uses mathematical expressions to describe the nonlinear transfer characteristic of the cascode modulated PA, is proposed. The behavior of the proposed baseband models is compared with the RF domain simulations in a 0.13μm CMOS process. View full abstract»

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  • A low voltage low power CMOS analog multiplier

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1393 KB) |  | HTML iconHTML  

    This paper presents a single low-voltage CMOS analog multiplier with low-power consumption. It consists of four voltage adders and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 0.9V supply voltage, the circuit has smaller than 1.8% linearity error and 0.88% THD under the maximum-scale input 400mVp-p at both inputs. The quiescent power consumption is 58μW and the -3dB bandwidth is 70MHz. View full abstract»

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  • An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1359 KB) |  | HTML iconHTML  

    In order to find relationships between Noise-Transfer-Function (NTF) characteristics and stability of a Incremental-Delta-Sigma ADC (I-DS-ADC) 40.000 different NTF has been investigated. A fast and easy to use criterion to determine, if an NTF of an I-DS-ADC of 4th-order is likely to be stable was found. The novel criterion is fast and easy to use and covers a much bigger variety of possible NTFs compared to recent criteria. View full abstract»

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  • A mixed mode design flow for multi GHz ADPLLs

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1472 KB) |  | HTML iconHTML  

    A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V. View full abstract»

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  • Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixers

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1365 KB) |  | HTML iconHTML  

    The conversion gain in mixers is traditionally calculated using a time-varying (TV) gain model and small signal excitation. In this paper we compare this approach with a brute force expansion of a polynomial model with multitone input. It is seen that the polynomial expansion preserves more information, and shows some distortion products that the time-varying model ignores. The polynomial expansion is used in Volterra-on-Harmonic Balance distortion contribution analysis to analyse both mixing and amplifying circuits. View full abstract»

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  • Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS

    Publication Year: 2011 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1251 KB) |  | HTML iconHTML  

    Two wideband Balun-LNA configurations have been designed in 65nm COMS technology. Both of them employ a single-to-differential (S-to-D) conversion topology composed of a common gate (CG) amplifying stage and a common source (CS) stage, providing output balancing and noise and distortion cancelling. One is inductorless and the other one exploits gain-boosting current-balancing topology. With 2.5V and 2.5V/1.8V supply the LNAs achieve voltage gains of 24.5dB and 22.8dB, noise figures of below or close to 3dB, input second-order intercept points (IIP2) of 31dB and 41.8dB, respectively. In addition, the sensitivity of IIP2 is deeply investigated. View full abstract»

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  • Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner

    Publication Year: 2011 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2259 KB) |  | HTML iconHTML  

    To enhance the performance of a switched-capacitor sigma-delta ADC we present a digitally trimmable on-chip voltage reference with a minimum step size in the range of 1-2mV@1.5-2.5V. Due to a multi-stage calibration scheme the output voltage of the reference could be additionally adjusted over a wide range of 500-700mV@1.7-2.1V. This can be useful to later adjust the reference levels in the sigma-delta modulator after design time (post-production). View full abstract»

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  • Dynamic bias schemes for class-C VCOs

    Publication Year: 2011 , Page(s): 1 - 4
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (815 KB) |  | HTML iconHTML  

    In class-C VCOs the trade-off between oscillation amplitude and start-up condition reduces the advantages of this topology with the respect to the traditional class-B operation. In this paper a dynamic bias scheme able to break this ultimate trade-off is presented. Two different topologies are reported. The first VCO uses an active current tail generator, while the second VCO has a passive resistive tail. Both solutions, simulated in a CMOS 65nm process, oscillate at 7.2GHz and show a phase noise of -126dBc/Hz @ 1MHz while drawing 11mA from a 1.2V supply voltage, resulting in a figure-of-merit of -191dBc/Hz. View full abstract»

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