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Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on

Date 9-12 Aug. 1998

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  • 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)

    Publication Year: 1998
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 1998, Page(s):v - xv
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    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s):620 - 622
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    Freely Available from IEEE
  • VHDL implementation of a 2-D uniform coefficient FIR filter

    Publication Year: 1998, Page(s):280 - 283
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1324 KB)

    This work presents a new VHDL design methodology and performance of a 2-D uniform finite impulse response (UCFIR) digital filter. The approach is analogous to that of the 2-D discrete cosine transform (DCT) in image processing applications. A set of 64 two-dimensional cosine basis functions are created by multiplying a horizontally oriented set of one-dimensional 8-point basis functions by a verti... View full abstract»

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  • Systems with symmetric impulse response

    Publication Year: 1998, Page(s):440 - 443
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    A class of low pass systems with maximum impulse response symmetry is presented. The optimization of the rational transfer function parameters is carried out for the functions of the third to the tenth order, with two to eight zeros. The time and frequency domain properties of the systems are given and compared to the known linear phase filter approximations View full abstract»

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  • Elements of general theory of null-balance circuits

    Publication Year: 1998, Page(s):110 - 113
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    The null-balance method of output indication is widely used in instrumentation techniques and sensor applications. Yet, the theorems and methods of general circuit theory that are the basis of the null-circuit analysis and design have nearly disappeared from the modern books on network theory. In this paper the elements of general theory of null-balance circuits are presented. The relationships be... View full abstract»

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  • Voice and video over ATM based cellular networks

    Publication Year: 1998, Page(s):157 - 160
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    New adaptation layer protocols (AAL-CU) have been proposed to transport multiplexed voice sources over ATM cellular networks. This paper studies the applicability of these proposed AAL-CU protocols to carry multiplexed voice and compressed video traffic. A simulation package has been developed to evaluate the performance of the proposed Ericsson, IBM and TISI protocols. Results indicate that the A... View full abstract»

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  • In vivo depth estimation of features in the chick eye by digital signal processing of ultrasonic pulse echoes

    Publication Year: 1998, Page(s):326 - 329
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    An existing biological instrumentation system which measures the depth of tissue boundaries in the chick eye has been modified to use National Instruments LabVIEW as a graphical interface for the operator. This system is used in a study to assess the effectiveness of pharmaceuticals designed to slow the progression of myopia, in which a high-speed data acquisition card digitizes the output of an u... View full abstract»

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  • Locally-clocked dynamic logic

    Publication Year: 1998, Page(s):18 - 21
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8... View full abstract»

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  • New approach to ideal inductors stored energy nature

    Publication Year: 1998, Page(s):199 - 202
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    Nonlinear load compensation required the definition of new concepts of electric power. On the basis of these new concepts the nature of the stored energy stored in ideal inductors is theoretically characterized in this work. Computer simulation and theory agree when applied to an isolated alternator View full abstract»

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  • Universal exponential function implementation using highly-linear CMOS V-I converters for dB-linear (AGC) applications

    Publication Year: 1998, Page(s):360 - 363
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    A universal exponential function generator is introduced which is implemented by low-voltage (⩽3 V) low-power CMOS widely-linear-input voltage-to-current converters. The Taylor's series expansion is used for the exponential function approach. The proposed exponential circuit is composed of a V-I squarer circuit, a linear V-I converter and a constant current biasing to synthesize the second-ord... View full abstract»

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  • Simultaneous optimization of boundary filters and stationary filters for paraunitary FIR filter banks

    Publication Year: 1998, Page(s):452 - 455
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    The optimization of two-band paraunitary finite impulse response (FIR) filter banks for finite-length signals is considered. Boundary filters which are optimal in a weighted mean square error (MSE) sense in the Fourier domain and the associated stationary filters are optimized simultaneously. Simulation results reveal that the maximally flat Daubechies filters are nearly optimal with respect to en... View full abstract»

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  • An efficient implementation of nested loop control instructions for super scalar processors

    Publication Year: 1998, Page(s):82 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    This paper presents a technique that makes efficient use of super scalar processor capabilities to optimize the execution of nested loop structures. By creating new global and local execution schedules, the linear dependencies inherent to the regular execution of the loop are removed and the degree of parallelism is increased. New compiler constructs allow the execution of the instructions accordi... View full abstract»

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  • A CMOS mixed signal simultaneous bidirectional signaling I/O

    Publication Year: 1998, Page(s):37 - 40
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Limited pin counts and achievable bandwidth have become a major limitation to achievable I/O speed of integrated circuits. Previously published current-mode techniques enable I/O circuits to achieve simultaneous bidirectional signaling. This maximizes data rate with minimal I/O power dissipation and minimal I/O pin count. A new I/O circuit fabricated in 2 μm CMOS is described in this work which... View full abstract»

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  • Integer pair representation of binary terms and equations

    Publication Year: 1998, Page(s):172 - 175
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    A new format to represent binary terms in a Boolean function, called the Integer Pair Representation (IPR) is proposed. This format uses an ordered pair of integers to compactly represent each cube of a Boolean function written as a sum-of-products in either canonical or non-canonical form. Properties of the representation are discussed and its advantages illustrated in the development of algorith... View full abstract»

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  • Low switching noise CMOS circuit design strategy based on regular self-timed structures

    Publication Year: 1998, Page(s):176 - 179
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    In this paper a new design strategy used to implement low switching noise digital circuits is presented. The switching noise reduction is achieved by controlling the shape of the switching current waveform of the CMOS logic circuits. Self-timed structures are required to obtain the wanted switching current waveform shape. Current limiters are also used to control the current waveform amplitude of ... View full abstract»

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  • Optimization of FIR digital filters over the canonical signed-digit coefficient space using genetic algorithms

    Publication Year: 1998, Page(s):456 - 459
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    In a recent paper a novel approach was presented for the restoration of canonical signed-digit (CSD) numbers to their correct format after the application of crossover and mutation operations in genetic algorithms. This paper is concerned with the development of a new technique for the optimization of FIR digital filters over the CSD coefficient space based on genetic algorithms. This optimization... View full abstract»

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  • Signal tracking fuzzy logic controller for DC-DC converters

    Publication Year: 1998, Page(s):306 - 309
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    A fuzzy logic controller is given for general DC-DC converters. The controller rule base comes from knowledge of converter operation. By controlling the switching duty cycle, a DC-DC converter can track a time varying reference signal having bandwidth beyond 20 KHz. Thus, the converter can be used as a high efficiency linear power amplifier with almost zero phase lag. Moreover, this performance is... View full abstract»

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  • Solving graph partitioning problem using genetic algorithms

    Publication Year: 1998, Page(s):302 - 305
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The graph partitioning problem (GPP) is one of the fundamental multimodal, combinatorial problems that has many applications in computer science. Many deterministic algorithms have been devised to obtain a good solution for the GPP. This paper presents new techniques for discovering more than one solution to this problem using genetic algorithms. The techniques used are based upon applying niching... View full abstract»

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  • Simulation of ungrounded shipboard power systems in PSpice

    Publication Year: 1998, Page(s):58 - 62
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Navy shipboard power systems (SPSs) have different characteristics when compared to utility power systems. To conduct system studies on SPSs, an effective simulation tool is required. PSpice is a very robust analog/digital circuit simulator, but it is rarely used in power system studies. This paper presents a PSpice methodology for modeling SPSs. Transient simulation results are also presented View full abstract»

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  • On a modified cepstral pitch control technique for the high quality text-to-speech type system

    Publication Year: 1998, Page(s):616 - 619
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    In the area of speech synthesis, the waveform coding methods are mainly used to maintain intelligibility and naturalness of synthetic speech. However, it is difficult to apply the waveform coding methods to the synthesis by rule since this methods does not separate both the excitation information and vocal tract information from a speech signal. This paper proposes a modified pitch alteration meth... View full abstract»

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  • Weaver architecture with bandpass delta-sigma A/D converters

    Publication Year: 1998, Page(s):530 - 533
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The bandpass delta-sigma A/D converters are placed into the Weaver architecture in this paper. One reason for this architecture is that using the noise shaping and oversampling method can minimize the quantization noise; the other is that this architecture increases the utilization of digital circuits and eliminates the passive RF image rejection filter. More programmability and flexibility can be... View full abstract»

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  • General methodologies to virtualize FPGAs in Hw/Sw systems

    Publication Year: 1998, Page(s):90 - 93
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    The computational needs of an increasing number of applications often require dedicated circuits. Configurable devices, like the Field-Programmable Gate Arrays (FPGAs), are one of the most used solutions to implement such a hardware support. However the size of the circuits that can be mapped on the currently available FPGAs at a medium or low cost is limited with respect to the high demand of sev... View full abstract»

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  • Design of interpolating filters

    Publication Year: 1998, Page(s):460 - 463
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    A new class of digital filters, which were termed interpolating filters, was recently introduced. The paper analyzes two methods for the design of these filters: (i) the cascade-type design, and (ii) the design based on a symbiotic composition of the interpolation and analog-filtering operators. It is proven that the latter is the method of choice View full abstract»

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  • A low voltage CMOS current conveyor for active filter design

    Publication Year: 1998, Page(s):142 - 145
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    A simple CMOS second generation negative current conveyor (CCII-) is presented which is suitable for low supply voltage operation. By restricting the CCII- to applications where the Y input is effectively referenced to signal ground, a greatly simplified circuit topology is realized. With only two devices stacked between the supply rails, low voltage operation is achieved. Internal negative feedba... View full abstract»

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