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2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

Date 3-5 Oct. 2011

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Displaying Results 1 - 25 of 68
  • [Front cover]

    Publication Year: 2011, Page(s): C1
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  • [Title page i]

    Publication Year: 2011, Page(s): i
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  • [Title page iii]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - x
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  • Message from the Symposium Chairs

    Publication Year: 2011, Page(s):xi - xii
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  • Organizing Committee

    Publication Year: 2011, Page(s): xiii
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  • Technical Program Committee

    Publication Year: 2011, Page(s): xiv
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  • Reviewers

    Publication Year: 2011, Page(s): xv
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  • Keynote speakers

    Publication Year: 2011, Page(s):xvi - xvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (155 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • On the Reliable Performance of Sequential Adders for Soft Computing

    Publication Year: 2011, Page(s):3 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (447 KB) | HTML iconHTML

    Addition is a significant operation in soft computing, several sequential adder designs have been proposed in the technical literature. These adders show different operational profiles, some of them are inspired by biological networks or the probabilistic nature of nanometric devices (such as the Lower-part OR Adder (LOA) and the Probabilistic Full Adder (PFA)). This paper deals with the reliabili... View full abstract»

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  • Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors

    Publication Year: 2011, Page(s):11 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    A low-overhead technique for correction of induced errors affecting algorithms and their data based on the concepts behind Hamming code is presented and evaluated. We go beyond Hamming code by computing the check digits as decimal sums, and using a checker algorithm to perform single error detection and correction and double error detection. This generalization allows for the protection of complex... View full abstract»

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  • Impact of Aging Phenomena on Soft Error Susceptibility

    Publication Year: 2011, Page(s):18 - 24
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (774 KB) | HTML iconHTML

    In this paper we address the issue of analyzing the effects of negative bias temperature instability (NBTI) on ICs' soft error susceptibility. We show that NBTI reduces significantly the critical charge of nodes of both combinational and sequential circuits during their in-field operation. Furthermore, we prove that combinational circuits present a higher relative reduction of node critical charge... View full abstract»

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  • An Area Effective Parity-Based Fault Detection Technique for FPGAs

    Publication Year: 2011, Page(s):27 - 33
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB) | HTML iconHTML

    Field programmable gate arrays (FPGAs) are highly successful platforms in a variety of niches, such as telecommunications and automotive applications. Their usage in critical systems for radiation environments, however, still depends on techniques able to provide increased reliability, since such devices are susceptible to single event upsets that may alter the specified functionality. Classical a... View full abstract»

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  • A Reliability-Aware Partitioner for Multi-FPGA Platforms

    Publication Year: 2011, Page(s):34 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    This paper presents a partitioning approach for reliable systems on multi-FPGA platforms. We propose a Mixed Integer Linear Programming model that distributes a system composed of self-checking and independently recoverable areas among the available devices, by achieving a uniform distribution and minimizing inter-FPGA communication. The partitioner takes into account also possible recovery action... View full abstract»

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  • Fine-Grained Software-Based Self-Repair of VLIW Processors

    Publication Year: 2011, Page(s):41 - 49
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB) | HTML iconHTML

    This paper describes a fine-grained software-based self-repair method for statically scheduled super scalar processors. An important property of this processor type is that for each operation of the executed program it is known in advance, which resources of the processor will be used by that operation. A scheduling algorithm is introduced that employs this knowledge in order to rearrange the oper... View full abstract»

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  • A New Algorithm for Post-Silicon Clock Measurement and Tuning

    Publication Year: 2011, Page(s):53 - 59
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (205 KB) | HTML iconHTML

    The number of speed paths in modern high-performance designs is in the range of millions. Due to unmodelled electrical effects, such as process variations and systemic delay defects, the speed paths are difficult to be measured accurately before the first silicon samples are available. To tolerate these unmodelled electrical effects, clock tuning elements are employed to aid the post-silicon clock... View full abstract»

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  • A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits

    Publication Year: 2011, Page(s):60 - 67
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    Over the last few decades, most quantitative measures of VLSI performance have improved by many orders of magnitude, this has been achieved by the unabated scaling of the sizes of MOSFETs. However, scaling also exacerbates noise and reliability issues, thus posing new challenges in circuit design. Reliability becomes a major concern due to many and often correlated factors, such as parameter varia... View full abstract»

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  • NBTI Monitoring and Design for Reliability in Nanoscale Circuits

    Publication Year: 2011, Page(s):68 - 76
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1320 KB) | HTML iconHTML

    Negative Bias Temperature Instability (NBTI) has become one of the major threats to circuit reliability in nanoscale-era. This paper presents a novel technique to monitor and tolerate NBTI in nanoscale circuits. First, it models NBTI impact on the gate output transition time, the simulation results show that NBTI can cause up to 8.56% increment to the transition time. Second, it presents a scheme ... View full abstract»

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  • Biased Voting for Improved Yield in Nanoscale Fabrics

    Publication Year: 2011, Page(s):79 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (626 KB) | HTML iconHTML

    Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that use majority voters to vote on the '0' or 1' outputs of redundant modules. Novel nanoscale computational fabrics employ new circuit and logic styles... View full abstract»

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  • CNT-count Failure Characteristics of Carbon Nanotube FETs under Process Variations

    Publication Year: 2011, Page(s):86 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1121 KB) | HTML iconHTML

    Carbon Nanotube Field Effect Transistors (CNFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. Chemical synthesis and lithography processes are exploited to fabricate CNFETs. Hence, in the presence of sub-wave length lithographic inaccuracies and chemical synthesis imperfections, CNT-count per CNFET deviates and may result in CNFET failure.... View full abstract»

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  • Optimal Test Set Selection for Fault Diagnosis Improvement

    Publication Year: 2011, Page(s):93 - 99
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (346 KB) | HTML iconHTML

    This paper proposes an approach for improving the diagnostic capability of a test-set used in the initial phases of the diagnosis process, when the system is quickly tested with a set of vectors aimed at making the fault observable with the smallest number of vectors. The selection policy identifies the optimal test set with respect to both minimal cardinality and maximum coverage, exploiting an I... View full abstract»

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  • Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits

    Publication Year: 2011, Page(s):103 - 111
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (345 KB) | HTML iconHTML

    Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicat... View full abstract»

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  • Reducing Test Power for Embedded Memories

    Publication Year: 2011, Page(s):112 - 119
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (453 KB) | HTML iconHTML

    With the increased number of embedded memories in mobile devices, minimizing the test power becomes a serious concern, especially when parallel testing is applied. Battery will be lost and the entire System on Chip (SoC) is subjected to be damaged if the peak power exceeds the power constraint. This paper proposes a new scheme to reduce the peak power during embedded SRAMs testing in mobile device... View full abstract»

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  • Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis

    Publication Year: 2011, Page(s):120 - 128
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (467 KB) | HTML iconHTML

    Post-silicon debugging process is aimed at locating errors not detected during the process of pre-silicon verification. Although in the post-silicon validation engineers can exploit the high speed of hardware prototype to exercise huge amount of test vectors, low level of real-time observability and controllability of signals inside the prototype is a big issue. Various Design for Debug (DFD) tech... View full abstract»

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