2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

7-10 Nov. 2011

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  • [Front matter]

    Publication Year: 2011, Page(s):1 - 2
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  • Executive Committee

    Publication Year: 2011, Page(s):1 - 7
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  • Foreword

    Publication Year: 2011, Page(s): 1
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  • Awards

    Publication Year: 2011, Page(s): 1
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  • Keynote address: Design of secure systems — Where are the EDA tools?

    Publication Year: 2011, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (134 KB) | HTML iconHTML

    Summary form only given. The design of security controllers, or more generally of microcontroller platforms implementing measures against hardware attacks, is still a very tedious handwork. Standardized and broadly available design tools as well as the necessary knowledge are rarely available and make secure hardware design a black art, known only within specialized companies building smart cards ... View full abstract»

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  • Panels [2 abstracts]

    Publication Year: 2011, Page(s): 1
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  • Table of contents

    Publication Year: 2011, Page(s):1 - 12
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  • Author index

    Publication Year: 2011, Page(s):1 - 10
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  • [Copyright notice]

    Publication Year: 2011, Page(s): 1
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  • Layout decomposition for triple patterning lithography

    Publication Year: 2011, Page(s):1 - 8
    Cited by:  Papers (43)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (748 KB) | HTML iconHTML

    As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (DPL). However, there is very little study on TPL layout decomposition. In this paper, we show that TPL layout decomposition is a more difficult problem than that for DPL. We then propose a general integer linear programmi... View full abstract»

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  • Optimal layout decomposition for double patterning technology

    Publication Year: 2011, Page(s):9 - 13
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (361 KB) | HTML iconHTML

    Double patterning technology (DPT) is regarded as the most practical solution for the sub-22nm lithography technology. DPT decomposes a single layout into two masks and applies double exposure to print the shapes in the layout. DPT requires accurate overlay control. Thus, the primary objective in DPT decomposition is to minimize the number of stitches (overlay) between the shapes in the two masks.... View full abstract»

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  • A framework for double patterning-enabled design

    Publication Year: 2011, Page(s):14 - 20
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1247 KB) | HTML iconHTML

    While the next generation of lithography systems is still under development, extending optical lithography using double patterning (DP) is the only solution to continue technology scaling. The biggest technical challenge of DP is the presence of mask-assignment conflicts in dense layers. In this paper, we propose a framework for DP conflict removal for standard cells. First, we offer an O(n) algor... View full abstract»

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  • Unequal-error-protection codes in SRAMs for mobile multimedia applications

    Publication Year: 2011, Page(s):21 - 27
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (792 KB) | HTML iconHTML

    In this paper, we introduce unequal-error-protection error correcting codes (UEPECCs) to improve SRAM reliability at low supply voltages for mobile multimedia applications. The fundamental premise for our work is that in multimedia applications, different bits in the same SRAM word are usually not equally significant, and hence deserve different protection levels. The key innovation in our work in... View full abstract»

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  • Detecting stability faults in sub-threshold SRAMs

    Publication Year: 2011, Page(s):28 - 33
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB) | HTML iconHTML

    Detecting stability faults has been a crucial task and a hot research topic for the testing of conventional super-threshold 6T SRAM in the past. When lowering the supply voltage of SRAM to the subthreshold region, the impact of stability faults may significantly change, and hence the test methods developed in the past for detecting stability faults may no longer be effective. In this paper, we fir... View full abstract»

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  • Pseudo-functional testing for small delay defects considering power supply noise effects

    Publication Year: 2011, Page(s):34 - 39
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (440 KB) | HTML iconHTML

    Detecting small delay defects (SDDs) has become increasingly important to address the quality and reliability concerns of integrated circuits. Without considering functional constraints in the circuits under test, however, existing techniques may generate test patterns that are functionally-unreachable. Such SDD patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths... View full abstract»

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  • A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding

    Publication Year: 2011, Page(s):40 - 47
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1359 KB) | HTML iconHTML

    A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the l... View full abstract»

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  • Bandwidth-aware reconfigurable cache design with hybrid memory technologies

    Publication Year: 2011, Page(s):48 - 55
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (597 KB) | HTML iconHTML

    In chip-multiprocessor (CMP) designs, limited memory bandwidth is a potential bottleneck of the system performance. New memory technologies, such as spin-torque-transfer memory (STT-RAM), resistive memory (RRAM), and embedded DRAM (eDRAM), are promising on-chip memory solutions for CMPs. In this paper, we propose a bandwidth-aware re-configurable cache hierarchy (BARCH) with hybrid memory technolo... View full abstract»

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  • Feedback control based cache reliability enhancement for emerging multicores

    Publication Year: 2011, Page(s):56 - 62
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1072 KB) | HTML iconHTML

    Focusing on data reliability, we propose a control theory centric approach designed to improve transient error resilience in shared caches of emerging multicores while satisfying performance goals. The proposed scheme takes, as input, two quality of service (QoS) specifications: performance QoS and reliability QoS. The first of these indicates the minimum workload-wide cache (L2) hit rate value ac... View full abstract»

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  • GPU programming for EDA with OpenCL

    Publication Year: 2011, Page(s):63 - 66
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (348 KB) | HTML iconHTML

    Graphical processing unit (GPU) computing has been an interesting area of research in the last few years. While initial adapters of the technology have been from image processing domain due to difficulties in programming the GPUs, research on programming languages made it possible for people without the knowledge of low-level programming languages such as OpenGL develop code on GPUs. Two main GPU ... View full abstract»

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  • A SimPLR method for routability-driven placement

    Publication Year: 2011, Page(s):67 - 73
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (841 KB) | HTML iconHTML

    Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance... View full abstract»

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  • Ripple: An effective routability-driven placer by iterative cell movement

    Publication Year: 2011, Page(s):74 - 79
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (5989 KB) | HTML iconHTML

    In this paper, we describe a routability-driven placer called Ripple. Two major techniques called cell inflation and net-based movement are used in global placement followed by a rough legalization step to reduce congestion. Cell inflation is performed in the horizontal and the vertical directions alternatively. We propose a new method called net-based movement, in which a target position is calcu... View full abstract»

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  • Routability-driven analytical placement for mixed-size circuit designs

    Publication Year: 2011, Page(s):80 - 84
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB) | HTML iconHTML

    Due to the significant mismatch between existing wirelength models and the congestion objective in placement, considering routability during placement is particularly significant for modern circuit designs. In this paper, a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs is proposed. Unlike most existing works which usually optimize routability by... View full abstract»

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  • PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs

    Publication Year: 2011, Page(s):85 - 90
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (476 KB) | HTML iconHTML

    Pulsed latches have emerged as a popular technique to reduce the power consumption and delay for clock networks. However, the current physical synthesis flow for pulsed latches still performs circuit placement and clock-network synthesis separately, which limits achievable power reduction. This paper presents the first work in the literature to perform placement and clock-network co-synthesis for ... View full abstract»

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  • Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories

    Publication Year: 2011, Page(s):91 - 94
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1397 KB) | HTML iconHTML

    Automated abstraction of large analog circuits greatly improves simulation time in custom analog design flows. Due to the high degree of variety of circuits this task is mainly a manual ad-hoc approach. This paper proposes an automated modeling approach for large scale analog circuits that produces compact expressions from a SPICE netlist. The presented method builds upon the state-of-the-art Traj... View full abstract»

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  • Optimal statistical chip disposition

    Publication Year: 2011, Page(s):95 - 102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (618 KB) | HTML iconHTML

    A chip disposition criterion is used to decide whether to accept or discard a chip during chip testing. Its quality directly impacts both yield and product quality loss (PQL). The importance becomes even more significant with the increasingly large process variation. For the first time, this paper rigorously formulates the optimal chip disposition problem, and proposes an elegant solution. We show... View full abstract»

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