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Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

21-21 Jan. 1999

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  • Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

    Publication Year: 1999
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    Freely Available from IEEE
  • Crosstalk reduction by transistor sizing

    Publication Year: 1999, Page(s):137 - 140 vol.1
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB)

    In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and validated by experiments. Then transistor sizing for timing and noise is discussed and solved using optimization techniques. Experimental results suggest that crosstalk violations can be removed by transistor sizing with very s... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):367 - 370
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    Freely Available from IEEE
  • Embedded tutorial: hardware/software codesign

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (49 KB)

    Due to the advance of VLSI technology, it is now possible to fabricate very complicated systems on a chip, which includes CPUs, peripheral circuits, and on-chip memories. These kinds of chips are very effective to implement various electronic systems such as for multimedia processing, communication, and real-time control. However there is a serious problem, called "design productivity crisis", to ... View full abstract»

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  • An efficient approach to constrained via minimization for two-layer VLSI routing

    Publication Year: 1999, Page(s):149 - 152 vol.1
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate View full abstract»

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  • Optimization of linear placements for wirelength minimization with free sites

    Publication Year: 1999, Page(s):241 - 244 vol.1
    Cited by:  Papers (37)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    We study a type of linear placement problem arising in detailed placement optimization of a given cell row in the presence of white-space (extra sites). In this single-row placement problem, the cell order is fixed within the row; all cells in other rows are also fixed. We give the first solutions to the single-row problem: (i) a dynamic programming technique with time complexity O(m2) ... View full abstract»

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  • Model order reduction of large circuits using balanced truncation

    Publication Year: 1999, Page(s):237 - 240 vol.1
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order of circuits before circuit-level simulation. In contrast to Pade-based algorithms which match the reduced order system with original system in some given frequencies, balanced realization based model algorithms provide a... View full abstract»

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  • Slicing floorplans with boundary constraint

    Publication Year: 1999, Page(s):17 - 20 vol.1
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to ha... View full abstract»

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  • Timing optimization of logic network using gate duplication

    Publication Year: 1999, Page(s):233 - 236 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    We present a timing optimization algorithm based on the concept of gate duplication on the technology-decomposed network. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum delay reduction with the minimum duplications. The p... View full abstract»

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  • Relaxed simulated tempering for VLSI floorplan designs

    Publication Year: 1999, Page(s):13 - 16 vol.1
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is des... View full abstract»

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  • Acceleration of linear block code evaluations using new reconfigurable computing approach

    Publication Year: 1999, Page(s):161 - 164 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper presents an approach to performing applications using reconfigurable computing (RC). Our RC approach is achieved by effective use of design automation systems. Logic circuits specialized for each individual application task are automatically implemented on FPGAs. Such circuits can quickly perform tasks that are time-consuming for general purpose computers. Decoding of binary linear bloc... View full abstract»

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  • FSM modeling of synchronous VHDL design for symbolic model checking

    Publication Year: 1999, Page(s):363 - 366 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    In this paper, we defined a new FSM model based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnecessary transition function, our model has much less states than Deharbe's mixed model. The experimental results demonstrate the model and modeling method can ma... View full abstract»

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  • Layout-based logic decomposition for timing optimization

    Publication Year: 1999, Page(s):229 - 232 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes dominated by the interconnect delay. In a traditional top-down design flow, logic synthesis algorithms optimize gate area or delay without accurate interconnect delay because of lack of physical design information. Thus, the effectiveness of the optimization techniques is limited. We integrate logic synthesis and phy... View full abstract»

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  • An SA-based nonlinear function synthesizer for linear analog integrated circuits

    Publication Year: 1999, Page(s):9 - 12 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Nonlinear functions can be approximated by the linear combination of base functions, which provides a road towards the analog synthesis. An improved Simulated Annealing Algorithm (SA) for nonlinear function approximation and a universal implementation of analog circuits are presented in this paper. Synthesis results demonstrate the validity and efficiency of the proposed approach View full abstract»

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  • An automatic router for the pin grid array package

    Publication Year: 1999, Page(s):133 - 136 vol.1
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical r... View full abstract»

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  • Node sampling technique to speed up probability-based power estimation methods

    Publication Year: 1999, Page(s):157 - 160 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces t... View full abstract»

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  • Analysing forced oscillators with multiple time scales

    Publication Year: 1999, Page(s):57 - 60 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner. This is made possible by a key new concept: that of warped time, related to normal time through separate time scales. Using warped time, we obtain a completely general formul... View full abstract»

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  • Fast Boolean matching under permutation using representative

    Publication Year: 1999, Page(s):359 - 362 vol.1
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion P-representative. If two functions have the same P-representative then they match. We develop a breadth-first search technique to quickly compute the P-representative. On an... View full abstract»

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  • Function smoothing with applications to VLSI layout

    Publication Year: 1999, Page(s):225 - 228 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    We present approximations to non-smooth continuous functions by differentiable functions which are parameterized by a scalar β>0 and have convenient limit behavior as β→0. For standard numerical methods, this translates into a tradeoff between solution quality and speed. We show the utility of our approximations for wirelength and delay estimations used by analytical placers for ... View full abstract»

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  • Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

    Publication Year: 1999, Page(s):153 - 156 vol.1
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher lev... View full abstract»

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  • Diagnosing single faults for interconnects in SRAM based FPGAs

    Publication Year: 1999, Page(s):283 - 286 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used. For non-adaptive test, eight programming steps is required to diagnose all the possible faults under the given single fault mode... View full abstract»

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  • Reduced-order modelling of time-varying systems

    Publication Year: 1999, Page(s):53 - 56 vol.1
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    We present a theory for reduced-order modelling of linear time-varying systems, together with efficient numerical methods for application to large systems. The technique, called TVP (Time-Varying Pade), is applicable to deterministic as well as noise analysis of many types of communication subsystems, such as mixers and switched-capacitor filters, for which existing model reduction techniques cann... View full abstract»

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  • Design re-use: where is the productivity going to come from?

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Semiconductor process geometries are shrinking and the available silicon capacity is growing at an amazing pace. Consumerization and convergence applications are causing tremendous time to market pressures, resulting in increased product complexity and reduced design cycle times. The gap between what can be built (silicon capacity) and what can be designed is widening. This `design productivity ga... View full abstract»

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  • A genetic algorithm based approach for multi-objective data-flow graph optimization

    Publication Year: 1999, Page(s):355 - 358 vol.1
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow graphs (DFG) which ensures that the correctness of algebraic transformations realized by the underlying genetic operators selection, recombination, and mutation is always preserved. We present substantial fitness functions for... View full abstract»

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  • New multilevel and hierarchical algorithms for layout density control

    Publication Year: 1999, Page(s):221 - 224 vol.1
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing (CIMP) which has varying effects on device and interconnect features, depending on local layout characteristics. To reduce manufacturing variation due to CMP and to improve yield and performance predictability, the layout needs to be made uniform with respect to certain density criteria, by inserting &ldq... View full abstract»

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