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Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date 21-21 Jan. 1999

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  • Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

    Publication Year: 1999
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    Freely Available from IEEE
  • Crosstalk reduction by transistor sizing

    Publication Year: 1999, Page(s):137 - 140 vol.1
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB)

    In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and validated by experiments. Then transistor sizing for timing and noise is discussed and solved using optimization techniques. Experimental results suggest that crosstalk violations can be removed by transistor sizing with very s... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):367 - 370
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    Freely Available from IEEE
  • Optimal evaluation clocking of self-resetting domino pipelines

    Publication Year: 1999, Page(s):121 - 124 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring cycle time to be the worst-case combinational logic delay around the ring. It is relatively immune to global clock skew, incurs no latch overhead, allows up to 50% time borrowing, and offers a robust way of prevent... View full abstract»

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  • Microprocessor technologies for the 21st century

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    In the past decade, computer technology advances have fundamentally changed practices in business and personal computing. With computer and communication networks extending connectivity to virtually every corner of the planet, the image of a wired world is no longer just a dream, it is a reality. The driving force behind this new computing revolution is rapid advance in processor technology-Moore'... View full abstract»

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  • Supplement to the Proceeding of Asia and South Pacific Design Automation Conference 1999

    Publication Year: 1999, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    First Page of the Article
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  • VCO jitter simulation and its comparison with measurement

    Publication Year: 1999, Page(s):85 - 88 vol.1
    Cited by:  Papers (21)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    We have simulated the phase noise of a voltage controlled oscillator (VCO) using an RF circuit simulator, SpectreRFTM. This simulator uses a variation of the periodic noise analysis first proposed by Okumura, et al (1993). It computes the power spectral density of the noise as a function of frequency. By assuming that only white noise sources are present in the oscillator, it is possibl... View full abstract»

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  • A new global routing algorithm independent of net ordering

    Publication Year: 1999, Page(s):245 - 248 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    We proposed a new global routing algorithm solving the net ordering problem. The algorithm uses random optimization methods to keep the equality of earlier routed nets and later routed nets in passing congested areas. It can find a solution independent of net ordering in short time. A global router is implemented in this method. Experiments show that the router performs much faster than Matula rou... View full abstract»

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  • Relaxed simulated tempering for VLSI floorplan designs

    Publication Year: 1999, Page(s):13 - 16 vol.1
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is des... View full abstract»

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  • Formal design verification for correctness of pipelined microprocessors with out-of-order instruction execution

    Publication Year: 1999, Page(s):177 - 180 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In this paper, we propose a verification method for pipelined microprocessors with out-of-order execution. We define a class of pipelined microprocessors with out-of-order execution and give a sufficient condition that guarantees the correctness of implementation. Each microprocessor in this class has a pipeline stg1,…,stgn such that the stages stgc ,&hellip... View full abstract»

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  • A single-chip CMOS CCD camera interface circuit with digitally controlled AGC

    Publication Year: 1999, Page(s):45 - 48 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    This paper describes a single-chip solution for CMOS CCD camera interface systems. The required AGC gain in the proposed circuit is controlled directly by digital bits without conventional extra DAC's. Nonlinear errors such as offsets in signal paths are automatically removed during black-level correction. The AGC outputs are transferred to a 10 b on-chip ADC. The prototype implemented in a 0.5 &m... View full abstract»

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  • Interconnect delay estimation models for synthesis and design planning

    Publication Year: 1999, Page(s):97 - 100 vol.1
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buffer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those fr... View full abstract»

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  • Layout-based logic decomposition for timing optimization

    Publication Year: 1999, Page(s):229 - 232 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes dominated by the interconnect delay. In a traditional top-down design flow, logic synthesis algorithms optimize gate area or delay without accurate interconnect delay because of lack of physical design information. Thus, the effectiveness of the optimization techniques is limited. We integrate logic synthesis and phy... View full abstract»

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  • Design re-use: where is the productivity going to come from?

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Semiconductor process geometries are shrinking and the available silicon capacity is growing at an amazing pace. Consumerization and convergence applications are causing tremendous time to market pressures, resulting in increased product complexity and reduced design cycle times. The gap between what can be built (silicon capacity) and what can be designed is widening. This `design productivity ga... View full abstract»

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  • Estimation of peak current through CMOS VLSI circuit supply lines

    Publication Year: 1999, Page(s):295 - 298 vol.1
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our final goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm of estimating the upper bound of the current, and uses an improved timed ATPG-based al... View full abstract»

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  • Solving the rectangular packing problem by an adaptive GA based on sequence-pair

    Publication Year: 1999, Page(s):181 - 184 vol.1
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In this paper, we propose a genetic algorithm (GA) to solve the rectangular packing problem (RP), in which the sequence-pair representation is adopted as the coding scheme of each chromosome. New genetic operators for RP are presented to explore the search space efficiently. The proposed GA has an adaptive strategy which dynamically selects an appropriate genetic operator during the GA execution d... View full abstract»

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  • Faster and better spectral algorithms for multi-way partitioning

    Publication Year: 1999, Page(s):81 - 84 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    In this paper two faster and better spectral algorithms are presented for the multi-way circuit partitioning problem with the objective of minimizing the scaled cost. The problem can be approximately transformed into the vector partitioning problem by mapping each circuit component to a multi-dimensional vector. The common key idea of our two algorithms for solving the vector partitioning problem ... View full abstract»

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  • Electrical design and design automation for packaging

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    One important challenge in the electrical design of electronic packaging is encountered in the many systems requiring processors operating at clock frequencies in the hundreds of Megahertz. The competition to provide higher performance computers results in an increasing number of processors in a system and these processors are running at faster clock frequencies. The package needs to support wider... View full abstract»

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  • An SA-based nonlinear function synthesizer for linear analog integrated circuits

    Publication Year: 1999, Page(s):9 - 12 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Nonlinear functions can be approximated by the linear combination of base functions, which provides a road towards the analog synthesis. An improved Simulated Annealing Algorithm (SA) for nonlinear function approximation and a universal implementation of analog circuits are presented in this paper. Synthesis results demonstrate the validity and efficiency of the proposed approach View full abstract»

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  • EDA Roadmap and Future VLSI Design Technology Enhancement

    Publication Year: 1999, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    First Page of the Article
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  • EDA Roadmap in Japan

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    The system LSI design in the future would be focused on an entire design procedure from algorithm design through physical implementation design. Revolutionary design methodologies are required from various aspects, such as software design accomplished in parallel with hardware design, built-in analog/sensor functionality of human interface and shorter time-to-market design style because of shorter... View full abstract»

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  • Recent advances in asynchronous design methodologies

    Publication Year: 1999, Page(s):253 - 259 vol.1
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    This tutorial surveys recent advances in asynchronous design methodologies. Whenever possible, actual design examples are used to present the methods. Three primary topics are discussed: (1) asynchronous controllers, (2) asynchronous datapaths, and (3) asynchronous systems. For asynchronous controllers, basic design styles and tools are presented. For asynchronous datapaths, basic issues in timed ... View full abstract»

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  • Data path synthesis for BIST with low area overhead

    Publication Year: 1999, Page(s):275 - 278 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper presents an attempt towards design quality improvement by incorporating of self-testability features during data path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to demo... View full abstract»

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  • Timing-driven bipartitioning with replication using iterative quadratic programming

    Publication Year: 1999, Page(s):105 - 108 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    We present an algorithm for solving a general min-cut, two-way partitioning problem subject to timing constraints. The problem is formulated as a constrained programming problem and solved in two phases: cut-set minimization and timing satisfaction. A mathematical programming technique based on iterative quadratic programming (TPIQ) is used to find an approximate solution to the constrained proble... View full abstract»

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  • Hazard-free synthesis and decomposition of asynchronous circuits

    Publication Year: 1999, Page(s):185 - 188 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms ha... View full abstract»

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