Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

21-21 Jan. 1999

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  • Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

    Publication Year: 1999
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    Freely Available from IEEE
  • Crosstalk reduction by transistor sizing

    Publication Year: 1999, Page(s):137 - 140 vol.1
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (411 KB)

    In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and validated by experiments. Then transistor sizing for timing and noise is discussed and solved using optimization techniques. Experimental results suggest that crosstalk violations can be removed by transistor sizing with very s... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):367 - 370
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    Freely Available from IEEE
  • Embedded tutorial: hardware/software codesign

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (49 KB)

    Due to the advance of VLSI technology, it is now possible to fabricate very complicated systems on a chip, which includes CPUs, peripheral circuits, and on-chip memories. These kinds of chips are very effective to implement various electronic systems such as for multimedia processing, communication, and real-time control. However there is a serious problem, called "design productivity crisis", to ... View full abstract»

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  • Clock period minimization of semi-synchronous circuits by gate-level delay insertion

    Publication Year: 1999, Page(s):125 - 128 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (308 KB)

    A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum de... View full abstract»

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  • A single-chip CMOS CCD camera interface circuit with digitally controlled AGC

    Publication Year: 1999, Page(s):45 - 48 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    This paper describes a single-chip solution for CMOS CCD camera interface systems. The required AGC gain in the proposed circuit is controlled directly by digital bits without conventional extra DAC's. Nonlinear errors such as offsets in signal paths are automatically removed during black-level correction. The AGC outputs are transferred to a 10 b on-chip ADC. The prototype implemented in a 0.5 &m... View full abstract»

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  • Symmetry detection for automatic analog-layout recycling

    Publication Year: 1999, Page(s):5 - 8 vol.1
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (272 KB)

    Layout symmetry is used to minimize the impact of mismatch on the performance of analog circuits. In this paper, an efficient algorithm is presented to detect automatically the mask layout symmetry. It consists of identifying signal nets, isolating circuit devices and detecting their symmetry, and finally, synthesizing the layout symmetry. Combined with layout compaction with symmetry constraints,... View full abstract»

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  • Universal switched-current integrator blocks for SI filter design

    Publication Year: 1999, Page(s):261 - 264 vol.1
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (264 KB)

    The switched-current (SI) circuit is a circuit technique which is able to realize analog sampled-data circuits with a standard CMOS technology. Among all the basic SI circuits, the memory cell circuit is the most primitive element. In this work, a practical SI memory cell which employs negative feedback circuitry and glitch reduction technique is first presented. Based on this basic cell, a univer... View full abstract»

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  • Supplement to the Proceeding of Asia and South Pacific Design Automation Conference 1999

    Publication Year: 1999, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (32 KB)

    First Page of the Article
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  • Motion estimator LSI for MPEG2 high level standard

    Publication Year: 1999, Page(s):41 - 44 vol.1
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    In this design, a dedicated motion estimation LSI of MPEG2 is presented. Combining the bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture as well as by using custom cell and full custom design methods the chip size becomes 4.8 mm×4.8 mm with 0.5 μm 2-level-metal CMOS technology. The test chip which works at 41.5 MHz, possesses a search range of ±67 for ... View full abstract»

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  • Slicing floorplans with boundary constraint

    Publication Year: 1999, Page(s):17 - 20 vol.1
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to ha... View full abstract»

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  • A scheduling method for synchronous communication in the Bach hardware compiler

    Publication Year: 1999, Page(s):193 - 196 vol.1
    Cited by:  Papers (2)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the... View full abstract»

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  • Electrical design and design automation for packaging

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (52 KB)

    One important challenge in the electrical design of electronic packaging is encountered in the many systems requiring processors operating at clock frequencies in the hundreds of Megahertz. The competition to provide higher performance computers results in an increasing number of processors in a system and these processors are running at faster clock frequencies. The package needs to support wider... View full abstract»

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  • Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

    Publication Year: 1999, Page(s):153 - 156 vol.1
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (420 KB)

    In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher lev... View full abstract»

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  • Optimal evaluation clocking of self-resetting domino pipelines

    Publication Year: 1999, Page(s):121 - 124 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (300 KB)

    We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring cycle time to be the worst-case combinational logic delay around the ring. It is relatively immune to global clock skew, incurs no latch overhead, allows up to 50% time borrowing, and offers a robust way of prevent... View full abstract»

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  • Recent advances in asynchronous design methodologies

    Publication Year: 1999, Page(s):253 - 259 vol.1
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (624 KB)

    This tutorial surveys recent advances in asynchronous design methodologies. Whenever possible, actual design examples are used to present the methods. Three primary topics are discussed: (1) asynchronous controllers, (2) asynchronous datapaths, and (3) asynchronous systems. For asynchronous controllers, basic design styles and tools are presented. For asynchronous datapaths, basic issues in timed ... View full abstract»

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  • Data path synthesis for BIST with low area overhead

    Publication Year: 1999, Page(s):275 - 278 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (324 KB)

    This paper presents an attempt towards design quality improvement by incorporating of self-testability features during data path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to demo... View full abstract»

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  • An automatic router for the pin grid array package

    Publication Year: 1999, Page(s):133 - 136 vol.1
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (332 KB)

    A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical r... View full abstract»

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  • An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection

    Publication Year: 1999, Page(s):37 - 40 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (392 KB)

    This paper describes an LSI implementation of a genetic algorithm (GA), called the Genetic Algorithm Accelerator (GAA) chip. The GAA chip is an LSI implementation of a GA, in which two types of crossover operators are supported, and the operator to be actually used in the algorithm is not fixed in advance, but dynamically selected for each pair of chromosomes in the algorithm execution. The GAA ch... View full abstract»

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  • Relaxed simulated tempering for VLSI floorplan designs

    Publication Year: 1999, Page(s):13 - 16 vol.1
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (416 KB)

    In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is des... View full abstract»

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  • Hierarchical floorplan design on the Internet

    Publication Year: 1999, Page(s):189 - 192 vol.1
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    With the proliferation of transistor count in VLSI design, more and more design groups try to figure out a way to efficiently combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical floorplan design can be adequately solved in the Internet environment. In this paper, we address the problem of area minimization floorplan design in the In... View full abstract»

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  • Package market segments and design challenges

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (60 KB)

    In the development of the 1997 edition of the National Technology Roadmap for Semiconductors (NTRS), the Roadmap Coordinating Group (RCG) recognized the needs of the semiconductor industry for larger chips having higher speed and power, and greater transistor density. The overall consensus is that the industry had over-run the present Roadmap Technology projections by about 1-2 years. From these p... View full abstract»

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  • An efficient approach to constrained via minimization for two-layer VLSI routing

    Publication Year: 1999, Page(s):149 - 152 vol.1
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate View full abstract»

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  • A new single-clock flip-flop for half-swing clocking

    Publication Year: 1999, Page(s):117 - 120 vol.1
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (296 KB)

    We propose a new flip-flop configuration which saves about 60% of total clocking power using a half-swing clock. To use the half-swing clock, level converters or special clock drivers are traditionally required and the power consumptions of this logic cannot be ignored. In the proposed scheme, only NMOS devices are clocked with a half-swing clock in order to make it operate without the level conve... View full abstract»

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  • Interconnect delay estimation models for synthesis and design planning

    Publication Year: 1999, Page(s):97 - 100 vol.1
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buffer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those fr... View full abstract»

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