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Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

21-21 Jan. 1999

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  • Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

    Publication Year: 1999
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  • Crosstalk reduction by transistor sizing

    Publication Year: 1999, Page(s):137 - 140 vol.1
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB)

    In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and validated by experiments. Then transistor sizing for timing and noise is discussed and solved using optimization techniques. Experimental results suggest that crosstalk violations can be removed by transistor sizing with very s... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):367 - 370
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    Freely Available from IEEE
  • EDA Roadmap in Japan

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    The system LSI design in the future would be focused on an entire design procedure from algorithm design through physical implementation design. Revolutionary design methodologies are required from various aspects, such as software design accomplished in parallel with hardware design, built-in analog/sensor functionality of human interface and shorter time-to-market design style because of shorter... View full abstract»

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  • Roadmap organization and activities in Japan

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    Describes the “technical difficulties to be solved and future technical directions” in various semiconductor technology areas. This activity is meaningful not only for semiconductor vendors but also for related industries, academia and research laboratories. In December 1998, STRJ (Semiconductor Technology Roadmap Committee of Japan) was established under EIAJ (Electronics Industry Ass... View full abstract»

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  • EDA Roadmap and Future VLSI Design Technology Enhancement

    Publication Year: 1999, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

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  • Power consumption in XOR-based circuits

    Publication Year: 1999, Page(s):299 - 302 vol.1
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using different delay models such as unit delay, fanout delay, and random delay in power estimation of XOR ... View full abstract»

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  • Supplement to the Proceeding of Asia and South Pacific Design Automation Conference 1999

    Publication Year: 1999, Page(s): 2
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  • Estimation of peak current through CMOS VLSI circuit supply lines

    Publication Year: 1999, Page(s):295 - 298 vol.1
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our final goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm of estimating the upper bound of the current, and uses an improved timed ATPG-based al... View full abstract»

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  • Node sampling technique to speed up probability-based power estimation methods

    Publication Year: 1999, Page(s):157 - 160 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces t... View full abstract»

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  • Minimization of free BDDs

    Publication Year: 1999, Page(s):323 - 326 vol.1
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Free BDDs (FBDDs) are an extension of ordered BDDs (OBDDs). FBDDs may have different orderings along each path. They allow a more efficient representation, while keeping (nearly) all of the properties of OBDDs. In some cases even an exponential reduction can be observed. In this paper we present for the first time an exact algorithm for finding a minimal FBDD representation for a given Boolean fun... View full abstract»

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  • Waveform relaxation of linear integral-differential equations for circuit simulation

    Publication Year: 1999, Page(s):61 - 64 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    We present waveform relaxation of linear integral-differential equations which occur in circuit simulation. We give sufficient conditions for convergence and numerical experiments to verify the theoretical results View full abstract»

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  • Symmetry detection for automatic analog-layout recycling

    Publication Year: 1999, Page(s):5 - 8 vol.1
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Layout symmetry is used to minimize the impact of mismatch on the performance of analog circuits. In this paper, an efficient algorithm is presented to detect automatically the mask layout symmetry. It consists of identifying signal nets, isolating circuit devices and detecting their symmetry, and finally, synthesizing the layout symmetry. Combined with layout compaction with symmetry constraints,... View full abstract»

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  • Realization of regular ternary logic functions using double-rail logic

    Publication Year: 1999, Page(s):331 - 334 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    In logic simulation, we often have to evaluate logic functions in the presence of unknown inputs. However, the naive method often produces incorrect values. In these cases, we can produce correct values by evaluating regular ternary logic functions instead of switching functions. This paper proposes a realization of regular ternary logic functions by using double-rail logic. This implementation re... View full abstract»

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  • A method for evaluating upper bound of simultaneous switching gates using circuit partition

    Publication Year: 1999, Page(s):291 - 294 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interco... View full abstract»

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  • Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

    Publication Year: 1999, Page(s):153 - 156 vol.1
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher lev... View full abstract»

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  • FSM modeling of synchronous VHDL design for symbolic model checking

    Publication Year: 1999, Page(s):363 - 366 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    In this paper, we defined a new FSM model based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnecessary transition function, our model has much less states than Deharbe's mixed model. The experimental results demonstrate the model and modeling method can ma... View full abstract»

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  • An SA-based nonlinear function synthesizer for linear analog integrated circuits

    Publication Year: 1999, Page(s):9 - 12 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Nonlinear functions can be approximated by the linear combination of base functions, which provides a road towards the analog synthesis. An improved Simulated Annealing Algorithm (SA) for nonlinear function approximation and a universal implementation of analog circuits are presented in this paper. Synthesis results demonstrate the validity and efficiency of the proposed approach View full abstract»

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  • Formal verification method for combinatorial circuits at high level design

    Publication Year: 1999, Page(s):319 - 322 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    In this paper, we propose a formal verification method for combinatorial circuits at high level design. The specification is described by both integer and Boolean variables for input and output variables, and the implementation is described by only Boolean variables. Our verification method judges the equivalence between the specification and the implementation by deciding the truth of the Presbur... View full abstract»

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  • Analysing forced oscillators with multiple time scales

    Publication Year: 1999, Page(s):57 - 60 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner. This is made possible by a key new concept: that of warped time, related to normal time through separate time scales. Using warped time, we obtain a completely general formul... View full abstract»

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  • Recent advances in asynchronous design methodologies

    Publication Year: 1999, Page(s):253 - 259 vol.1
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    This tutorial surveys recent advances in asynchronous design methodologies. Whenever possible, actual design examples are used to present the methods. Three primary topics are discussed: (1) asynchronous controllers, (2) asynchronous datapaths, and (3) asynchronous systems. For asynchronous controllers, basic design styles and tools are presented. For asynchronous datapaths, basic issues in timed ... View full abstract»

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  • An adaptive BIST to detect multiple stuck-open faults in CMOS circuits

    Publication Year: 1999, Page(s):287 - 290 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average le... View full abstract»

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  • Technology mapping for low power

    Publication Year: 1999, Page(s):145 - 148 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several research attentions. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. In this paper, we propose a pattern oriented power modeling for improved technology mapping. We first perform a... View full abstract»

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  • Fast Boolean matching under permutation using representative

    Publication Year: 1999, Page(s):359 - 362 vol.1
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion P-representative. If two functions have the same P-representative then they match. We develop a breadth-first search technique to quickly compute the P-representative. On an... View full abstract»

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  • A new pipelined architecture for fuzzy color correction

    Publication Year: 1999, Page(s):209 - 212 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner into that of an output device such as the printer, is important for multimedia applications. In this paper, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm proposed by Jer-Min Jou et al. (1998) to meet the speed requirement of time-critical appli... View full abstract»

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