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2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems

Date 23-26 Oct. 2011

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Displaying Results 1 - 25 of 99
  • [Title page]

    Publication Year: 2011, Page(s):i - ii
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  • Welcome message

    Publication Year: 2011, Page(s):iii - iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - vii
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  • Program

    Publication Year: 2011, Page(s):viii - xii
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  • Chairs EC

    Publication Year: 2011, Page(s): xiii
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  • EPEPS-2011 Technical Program Committee (TPC)

    Publication Year: 2011, Page(s): xiv
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  • All sponsor page

    Publication Year: 2011, Page(s): xv
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  • Gold Rambus

    Publication Year: 2011, Page(s): xvi
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  • Silver sponsor Apache

    Publication Year: 2011, Page(s): xvii
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  • Silver Agilent and 3 DIC-RC

    Publication Year: 2011, Page(s): xviii
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  • Silver Mentor and ASE

    Publication Year: 2011, Page(s): xix
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  • Silver Nimbic and TI

    Publication Year: 2011, Page(s): xx
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  • Exhibitors

    Publication Year: 2011, Page(s):xxi - xxii
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  • Power integrity in high-speed designs (M-IV)

    Publication Year: 2011, Page(s):1 - 2
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  • Plane bounce in high-speed single-ended signaling I/O interfaces

    Publication Year: 2011, Page(s):3 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1499 KB) | HTML iconHTML

    Single-ended signaling is a popular choice for memory interface designs, due to its low pin-count requirement and slow DRAM process technology. Single-ended signaling requires a good current return path, in order to maintain high signal quality. Commonly used single-ended signaling schemes require both power and ground current return paths. In high-density memory interface systems, not all of the ... View full abstract»

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  • Practical aspects of modeling apertures for signal and power integrity co-simulation

    Publication Year: 2011, Page(s):7 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1660 KB) | HTML iconHTML

    When the return path of a signal is not continuous, unwanted noise will couple to the return current, leading to worsening of the signal waveform. To prevent such a signal integrity issue, a thorough understanding of the physics of the return path discontinuity (RPD) is critical. This paper presents analysis and quantification of the impact of RPDs in the presence of a power delivery network The s... View full abstract»

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  • Verification of novel technology for power integrity on 16-channel 3Gbps circuit boards

    Publication Year: 2011, Page(s):11 - 14
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1758 KB) | HTML iconHTML

    Power integrity (PI) for recent electronics circuits and systems is the most important technological issue in the field and has been addressed in important papers through several approaches [1][2]. The latest concept of the best PI condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found... View full abstract»

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  • Design strategies for processor, chip/package co-design (M-VI)

    Publication Year: 2011, Page(s):15 - 16
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  • Deriving voltage tolerance specification for processor circuit design

    Publication Year: 2011, Page(s):17 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (594 KB) | HTML iconHTML

    A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous ... View full abstract»

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  • Early stage chip/package/board co-design techniques for system-on-chip

    Publication Year: 2011, Page(s):21 - 24
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (421 KB) | HTML iconHTML

    With the advancements in semiconductor process technologies in recent years, many circuits are mounted on small dies and the number of interface pins has rapidly increased. The demand for smaller chip/package sizes has come about in order to reduce costs. This paper describes the early stage chip/package/board co-design techniques which reduce chip and package size by cutting down the number of PD... View full abstract»

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  • Novel RF and chip-to-chip interconnects (M-VII)

    Publication Year: 2011, Page(s):25 - 26
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  • High-density silicon carrier transmission line design for chip-to-chip interconnects

    Publication Year: 2011, Page(s):27 - 30
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (782 KB) | HTML iconHTML

    Two differential stripline configurations with pitches of 8μm and 22μm are designed for ultra dense interconnect on silicon carrier. The transmission lines are implemented using four wiring levels to support chip-to-chip communication at 11.5Gb/s data rate over 2cm without equalization. Loss characteristics are extracted from test coupons with good model-to-hardware correlation. Impe... View full abstract»

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  • Wireless RF data communications using 60 GHz antennas in Multi-Core systems

    Publication Year: 2011, Page(s):31 - 34
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (313 KB) | HTML iconHTML

    Free space wireless transmission via the 60 GHz antenna in the Multi-Chip Multi-Core (MCMC) architecture is proposed in this paper. Antenna in package (AiP) solution is chosen as the 60GHz antenna configuration and the antenna is designed based on low temperature co-fired ceramic (LTCC) superstrate that could connect to the silicon circuitry via the flip- chip technology. The designed antenna havi... View full abstract»

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  • Electrical performance of vertical natural capacitor for RF system-on-chip in 32-nm technology

    Publication Year: 2011, Page(s):35 - 38
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1005 KB) | HTML iconHTML

    Radio frequency system-on-chips (RF SoC) require high quality passive devices such as capacitors. We comprehensively studied the vertical natural capacitors (VNCAP) made of CMOS back-end-of-lines (BEOL) in 32-nm technology. We used electromagnetic simulation and a Pi-type equivalent circuit model for the study of the VNCAP, and reported its electrical characteristics including the scattering param... View full abstract»

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  • Macromodeling and circuit analysis (M-IX)

    Publication Year: 2011, Page(s):39 - 40
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