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SOC Conference (SOCC), 2011 IEEE International

Date 26-28 Sept. 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • Message from general chairs

    Publication Year: 2011, Page(s):1 - 2
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  • Message from technical chairs

    Publication Year: 2011, Page(s):1 - 2
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  • Program-at-a glance

    Publication Year: 2011, Page(s):1 - 2
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  • 2011 SOCC Organizing Committee

    Publication Year: 2011, Page(s):1 - 3
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  • List of reviewers

    Publication Year: 2011, Page(s): 1
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  • Table of contents

    Publication Year: 2011, Page(s):1 - 8
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  • Author index

    Publication Year: 2011, Page(s):1 - 4
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  • Keynote speaker

    Publication Year: 2011, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (223 KB)

    Summary form only given. SoCC started out as the IEEE ASIC Conference, moved to ASIC/SOC, and then to its current title SoCC. As the number of transistors on a chip has increased, designers have found it useful to include, in addition to the processor, a lot of system stuff that is in many ways orthogonal to the processor. We will soon reach the point where each chip will contain 50 billion transi... View full abstract»

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  • Plenary speaker

    Publication Year: 2011, Page(s): 2
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    Nanosystems - based on the systematic application of nano-technologies - will create a large market of applications and a renewed perspective for electronic design and manufacturing companies. Such systems will be the fundamental building blocks of wearable and ambient systems, to gather and integrate heretogeneous data in real time and to operate and communicate in a wireless and ultra low power ... View full abstract»

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  • Plenary speaker

    Publication Year: 2011, Page(s):3 - 4
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    Ageing population and decreasing birth rates are common phenomena taking place around the world. These two factors have increased the rise of chronic diseases and have led to uneven distribution of medical resources as well as the emergence of basic health care demands in emerging markets. Looking forth to the future, it is projected that telecare will become a major means of coping with such issu... View full abstract»

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  • Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore

    Publication Year: 2011, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB) | HTML iconHTML

    Summary form only given. Microfluidics-based biochips (or lab-on-chip) are revolutionizing laboratory procedures in molecular biology, and leading to a convergence of information technology with biochemistry and nanoelectronics. Advances in microfluidics technology offer exciting possibilities for high-throughput DNA sequencing, protein crystallization, drug discovery, immunoassays, neo-natal and ... View full abstract»

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  • Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips

    Publication Year: 2011, Page(s):6 - 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1099 KB) | HTML iconHTML

    Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. The “digital” biochips are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the arra... View full abstract»

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  • Recent research and emerging challenges in design and optimization for digital microfluidic biochips

    Publication Year: 2011, Page(s):12 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1629 KB) | HTML iconHTML

    Advances in droplet-based digital microfluidic biochips (DMFBs) have led to the emergence of biochips for automating laboratory procedures in biochemistry and molecular biology. These devices enable the precise control of microliter of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and integrate various bioassay operations, such as sample preparation,... View full abstract»

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  • “Post silicon debug of SOC designs”

    Publication Year: 2011, Page(s): 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB) | HTML iconHTML

    Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to fin... View full abstract»

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  • An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions

    Publication Year: 2011, Page(s):19 - 23
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1787 KB) | HTML iconHTML

    In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime a... View full abstract»

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  • A gate sizing method for glitch power reduction

    Publication Year: 2011, Page(s):24 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (597 KB) | HTML iconHTML

    Due to the difficulty in estimating dynamic power at the gate level, a quantity called power metric and its efficient calculation method are introduced in this work. Based on the proposed power metric, a heuristic gate sizing algorithm for glitch power reduction is proposed for semi-custom design. The proposed heuristic algorithm minimizes the total power metric of a circuit. According to the expe... View full abstract»

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  • Novel adaptive keeper LBL technique for low power and high performance register files

    Publication Year: 2011, Page(s):30 - 35
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    This paper develops a novel adaptive keeper local bit line (LBL) technique to achieve low power and high performance register files design. To avoid increasing the implementation hardware overhead, the proposed technique employs a clock-combined unit to generate the body voltage of keeper. We evaluate the effectiveness of the proposed technique in a two-cycle 64-entries×32 b register file d... View full abstract»

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  • Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system

    Publication Year: 2011, Page(s):36 - 41
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1791 KB) | HTML iconHTML

    The Synchronous Transfer Architecture is a low power architecture of VLIW processor, which enables the direct data routing through buffered output ports of functional units. To improve the system efficiency of STA, in this paper we propose a novel approach to integrate compiler techniques with architecture exploration: A fuzzy control system is implemented to help the compiler back-end determine t... View full abstract»

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  • A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

    Publication Year: 2011, Page(s):42 - 47
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1258 KB) | HTML iconHTML

    A clock skew-compensation and/or duty-cycle-correction circuit (CSADC) is indispensably required to maximize the performance of a synchronous double edge clocking system. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more design complexity. A compact delay-recycled CSA... View full abstract»

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  • A low-power all-digital phase modulator pair for LINC transmitters

    Publication Year: 2011, Page(s):48 - 51
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (791 KB) | HTML iconHTML

    This paper presents a low-power all-digital phase modulator (PM) pair to generate constant-envelope signals for LINC transmitters. To reduce the power overhead, an open-loop delay line based phase shifter with a continuous locking scheme is adopted for the PM design. This design is implemented by 90 nm CMOS technology with active area of 0.1892 mm2. The PM provides 8-bit resolution with... View full abstract»

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  • A low power wide tuning range VCO with coupled LC tanks

    Publication Year: 2011, Page(s):52 - 56
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    A 12GHz VCO fabricated in a 0.18μm SiGe BiCMOS technology with only CMOS devices, is presented. To improve tuning range and phase noise, a technique using strongly magnetic coupled LC tanks with fixed and tunable capacitive elements is proposed. The VCO achieves wide tuning range of 4.3GHz (36%) with only 4.5mW power consumption. The proposed VCO including buffer stage occupies a chip area ... View full abstract»

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  • A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization

    Publication Year: 2011, Page(s):57 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB) | HTML iconHTML

    This paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (VDDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) VDDmin of a FF is stochastically modeled by a log-normal distri... View full abstract»

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  • A silicon core for an acoustic archival tag

    Publication Year: 2011, Page(s):63 - 69
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2313 KB) | HTML iconHTML

    This paper presents a tiny 0.5 μm CMOS chip, which forms the core of an acoustic archival tag. The 1.5 × 1.5 mm die enables tracking of small fishes by detecting a specific sound signature emitted by moored sources. It also houses a temperature sensor and a pressure sensor interface and controls all internal and external communication. The tag consumes 6 μW in standby mode and... View full abstract»

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  • A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations

    Publication Year: 2011, Page(s):70 - 75
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB) | HTML iconHTML

    Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under... View full abstract»

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