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Advanced Packaging, IEEE Transactions on

Issue 4 • Date Nov. 2010

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Displaying Results 1 - 25 of 44
  • Table of contents

    Page(s): C1 - 753
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  • IEEE Transactions on Advanced Packaging publication information

    Page(s): C2
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  • Editorial CPMT Society to Merge Transactions in 2011

    Page(s): 754 - 755
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  • Our Thanks to Reviewers IEEE Transactions on Advanced Packaging

    Page(s): 756 - 757
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  • Foreword Special Section on Recent Progress in Electrical Modeling and Simulation of High-Speed ICs and Packages

    Page(s): 758 - 759
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  • Waveform Relaxation Time Domain Solver for Subsystem Arrays

    Page(s): 760 - 768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (927 KB) |  | HTML iconHTML  

    In this paper we present a waveform relaxation approach for the transient analysis of 3-D electromagnetic problems using the partial element equivalent circuit (PEEC) method. Relying on weaker couplings among separated systems, a waveform relaxation scheme is proposed to accelerate the transient analysis of large electromagnetic problems. The results are compared with those obtained using a conventional PEEC formulation. They exhibit a significant speed-up while preserving the solution accuracy. View full abstract»

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  • A Flexible Time-Stepping Scheme for Hybrid Field-Circuit Simulation Based on the Extended Time-Domain Finite Element Method

    Page(s): 769 - 776
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (886 KB) |  | HTML iconHTML  

    This paper describes a flexible time-stepping scheme for a recently developed hybrid field-circuit solver based on the extended time-domain finite element method (TDFEM) to alleviate the limitation on the use of a system-wide global time-step size. The proposed time-stepping scheme generalizes the strict synchronous coupling mechanism between the FEM and circuit subsystems and allows the signals in the different subsystems to be tracked and sampled at different time-step sizes. The signals from a slow subsystem with a larger time-step size are extrapolated, when necessary, for updating the signals in a fast subsystem with a smaller time-step size. The capability of the hybrid field-circuit solver with the proposed time-stepping scheme is further enhanced by the application of a tree-cotree splitting technique to the FEM subsystem, which helps reduce the iteration count per time step for a preconditioned iterative solution when the time-step size of the FEM subsystem becomes relatively large. With the flexibility of choosing subsystem-specific time-step sizes, the proposed time-stepping scheme improves the computational efficiency of the existing TDFEM-based hybrid field-circuit solver especially when the computational cost associated with the slow subsystems is much higher than that associated with the fast subsystems. View full abstract»

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  • A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures

    Page(s): 777 - 786
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    To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost. View full abstract»

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  • A Novel High-Capacity Electromagnetic Compression Technique Based on a Direct Matrix Solution

    Page(s): 787 - 793
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (502 KB) |  | HTML iconHTML  

    Electromagnetic solvers based on integral equations in conjunction with the method of moments or the partial element equivalent circuit method (PEEC) proved to be popular because of their efficiency and accuracy. There is one serious drawback of the integral equation approach: it often leads to a linear system involving a full matrix. Many efficient approaches have been proposed to overcome this, largely based on compressing the matrix-vector product operation and using an iterative solver. Iterative EM solvers, however, suffer from slow convergence, which does not have a totally reliable method to address; further, large multiple right-hand sides significantly increase the solving time. In this paper, we present a novel method to compress low rank sub-block matrixes into sparse matrix to be used with a direct sparse matrix solver to obtain an efficient high-capacity electromagnetic solver based on an integral equation formulation. The full-rank system matrix is represented in a hierarchical matrix format that has its sub-matrixes compressed with numerically controllable accuracy; it is then analytically converted to a sparse matrix which is further solved by a direct sparse matrix solver. Analytically this method results in O(N (log N)2) complexity for computing the inverse of a hierarchical matrix presented in Fig. 2 where N is the number of unknowns. View full abstract»

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  • An LU Decomposition Based Direct Integral Equation Solver of Linear Complexity and Higher-Order Accuracy for Large-Scale Interconnect Extraction

    Page(s): 794 - 803
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1015 KB) |  | HTML iconHTML  

    A fast LU factorization of linear complexity is developed to directly solve a dense system of linear equations for the capacitance extraction of any arbitrary shaped 3-D structure embedded in inhomogeneous materials. In addition, a higher-order scheme is developed to achieve any higher-order accuracy for the proposed fast solver without sacrificing its linear computational complexity. The proposed solver successfully factorizes dense matrices that involve more than one million unknowns in fast CPU run time and modest memory consumption. Comparisons with state-of-the-art integral-equation-based capacitance solvers have demonstrated its clear advantages. In addition to capacitance extraction, the proposed LU solver has been successfully applied to large-scale full-wave extraction. View full abstract»

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  • Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions

    Page(s): 804 - 817
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    This paper proposes an efficient method to model through-silicon via (TSV) interconnections, an essential building block for the realization of silicon-based 3-D systems. The proposed method results in equivalent network parameters that include the combined effect of conductor, insulator, and silicon substrate. Although the modeling method is based on solving Maxwell's equation in integral form, the method uses a small number of global modal basis functions and can be much faster than discretization-based integral-equation methods. Through comparison with 3-D full-wave simulations, this paper validates the accuracy and the efficiency of the proposed modeling method. View full abstract»

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  • A Markov Chain Based Hierarchical Algorithm for Fabric-Aware Capacitance Extraction

    Page(s): 818 - 827
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    In this paper, we propose a hierarchical algorithm to compute the 3-D capacitances of a large number of topologically different layout configurations that are all assembled from the same basic layout motifs. Our algorithm uses the boundary element method in order to compute a Markov transition matrix (MTM) for each motif. The individual motifs are connected together by building a large Markov chain. Such Markov chain can be simulated extremely efficiently using Monte Carlo simulations (e.g., random walks). The main practical advantage of the proposed algorithm is its ability to extract the capacitance of a large number of layout configurations in a complexity that is basically independent of the number of configurations. For instance, in a large 3-D layout example, the capacitance calculation of 1000 different configurations assembled from the same motifs is accomplished in the time required to solve independently two configurations, i.e., a 500 × speedup. View full abstract»

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  • Physics-Based Gridding for Electrical Package Analysis Codes

    Page(s): 828 - 838
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (818 KB) |  | HTML iconHTML  

    This paper describes techniques and advances for mesh generation and refinement for the analysis of electrical package structures. After a brief review of meshing techniques, a physically based justification is provided for the basic elements of gridding required to accurately represent the following physical issues: edge-effects, projection gridding for signal return currents, conductor proximity, skin-effect, frequency effects, and dielectrics. These individual gridding components are then incorporated into a comprehensive, global algorithm. Many other meshing issues are addressed, including constraints associated with the underlying electromagnetic calculation kernel, removal of superfluous grid lines, assuring symmetric results for symmetric structures, and consistency related to causality and nonphysical effects. A number of 2D and 3D examples are taken from various codes developed by the author and novel techniques are given for effectively gridding 2D structures having even extreme geometric aspect ratios. View full abstract»

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  • Random Rough Surface Effects on Wave Propagation in Interconnects

    Page(s): 839 - 856
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1297 KB) |  | HTML iconHTML  

    To address the rough surface effects in high-speed interconnects on printed circuit boards (PCBs) and microelectronic packages, we study the electromagnetic wave propagation in a rough surface environment. In our model, the rough surface is characterized by a stochastic random process with correlation function or spectral density. This paper reviews the analytical theory, numerical simulations and experimental results based on such a model. We describe the rough surface characterization and the extraction of roughness parameters from 3D profile measurements. Initially we study the 2D case with the rough surface height function varying in only one horizontal direction and consider the case of plane wave incidence. Analytic second-order small perturbation method (SPM2) was used to obtain simple closed-form expressions for the absorption enhancement factor. The numerical transfer matrix (T-matrix) method and the method of moments (MoM) were also used. We next consider the case of the 3D problem with the rough surface height varying in both horizontal directions. We also used SPM2 to obtain a simple closed form expression for the enhancement factor. In interconnect problems, electromagnetic (EM) waves propagate in a guided wave environment. Thus, we next considered a waveguide model to study the effects of random roughness on wave propagation and compare with results from the plane wave formulation. Analytic SPM2 and numerical finite element method (FEM) with mode matching were used to obtain the enhancement factor. We also describe experimental results and correlation with the theoretical models. Finally, we explain how the enhancement factor concept used throughout lends itself to direct inclusion of rough surface effects in a wide variety of modeling problems. View full abstract»

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  • Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems

    Page(s): 857 - 867
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    Accurate modeling of transmission lines becomes increasingly important in high-speed interconnect system design. However, it is rather difficult to obtain broadband transmission line models, in particular using frequency-domain measurements. This paper points out two potential accuracy issues. First, inaccurate DC values of the frequency-domain data cause a severe error in the time-domain simulations. Second, it is difficult to characterize the characteristic impedance over a wide frequency range due to the reflection caused by the port discontinuities. This paper proposes the combination of both time and frequency measurement data to mitigate the DC accuracy issue. For the characteristic impedance model, a new de-embedding technique is presented to mitigate the port discontinuity issue. Several numerical examples, such as MCM-L coplanar lines and package microstrip lines, are studied to validate the accuracy of the proposed method. View full abstract»

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  • A Pluggable Large Core Step Index Plastic Optical Fiber With Built-In Mode Conditioners for Gigabit Ultra Short Reach Networks

    Page(s): 868 - 875
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (896 KB) |  | HTML iconHTML  

    Large core step-index plastic optical fibers (SI-POF) are bandwidth limited due to their high modal dispersion and coupling loss at the receiver. To date, the large core SI-POF are typically deployed up to 150 Mb/s applications. This paper reports the transmission of 2.5 Gb/s on 980 μm core step-index plastic optical fiber with fiber-based mode conditioning elements that are part of the connector assembly. The built-in mode conditioners are tapered fiber tips that provide restricted mode launching at transmitter and mode filtering at the receiver side. The structures, at the tip of POF, are optimized by optical simulations and fabricated using laser fusion process. The connector assembly is realized by precisely encapsulating the mode conditioners with a metallic ferrule and positioned using optical grade epoxies. These plug-in modules are inserted to a typical SFP transceiver LC connector receptacle and characterized for gigabit rates. View full abstract»

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  • Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate

    Page(s): 876 - 882
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1329 KB) |  | HTML iconHTML  

    Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher input/outputs (I/O) counts, pushing packaging towards higher density architectures. In the next two to three years, the I/O pitch will fall within 100 μm for area array die and 30 μm for periphery die. That raises an important question to the packaging industry: How will the rapid shrinkage of the I/O pitch affect the package substrate for chip attaching? The answer is sub-10 micron copper line technology. Theoretical and experimental studies on the limitations of using mercury i-line ultraviolet photolithography have been carried at the Packaging Research Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated for flip chip attaching by using semi-additive metallization process. View full abstract»

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  • A 3-D X-Band T/R Module Package With an Anodized Aluminum Multilayer Substrate for Phased Array Radar Applications

    Page(s): 883 - 891
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1848 KB) |  | HTML iconHTML  

    This paper presents the design and development of a compact 3-D transmit/receive (T/R) module with a selectively anodized aluminum multilayer package for X-band phased array radar applications. The proposed multilayer package consists of anodized aluminum substrates and vertical interconnects with embedded vias. The proposed package platform is based on thick anodized aluminum oxide layers and active bare chips directly mounted on bulk aluminum substrates for high electrical isolation and an effective heat sink. With its combination of thin-film embedded passive components and multilayer structure, the proposed module features a compact size of 20 mm × 20 mm, with a package height of 3.7 mm. To transfer radio-frequency (RF) signals vertically, we used coaxial hermetic seal vias with characteristic 50 Ω impedances and embedded anodized aluminum vias with a solder ball attachment and flip-chip bonding. The optimized vertical interconnect structure demonstrates RF characteristics with an insertion loss of less than 1.55 dB and a return loss of less than 12.25 dB over a broad bandwidth ranging from 0.1 to 10 GHz. The fabricated X-band 3-D T/R module has a maximum transmit output power of 39.81 dBm (9.5 W), a maximum transmit gain of 41.25 dB, and a receive gain of 19.15 dB over the 9-10 GHz frequency band. The RF-signal phase amplitude control is achieved by means of a 6 bit phase shifter with an rms accuracy of more than 5° and a gain setting range of 24 dB with an rms accuracy of more than 1.5 dB. The proposed multilayer aluminum package has the advantages of reducing the module size, decreasing the cost, and managing the thermal problem for X-band high-power T/R module package applications. View full abstract»

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  • Interfacial Design of Anisotropic Conductive Adhesive Based Interconnects Using Molecular Wires and Understanding of Their Electrical Conduction

    Page(s): 892 - 898
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    Anisotropic conductive adhesives (ACAs) have been considered a promising interconnect material for next generation high performance devices. However, high joint resistance and low current carrying capability of ACA interconnects have been the limitations to utilizing ACAs in high power devices. In this study, we have introduced conjugated dithiols into ACA formulations to create molecular wire junctions between conductive fillers and metal pads as a means to facilitate the electron transport through the ACA joints. With the introduction of molecular wires, there is evidence of measured improvements in both the electrical conductivity and current carrying capability. The factors leading to these improvements in electrical properties are also discussed. View full abstract»

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  • A Homogeneous Electrically Conductive Silver Paste

    Page(s): 899 - 903
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1719 KB) |  | HTML iconHTML  

    A homogeneous electrically conductive silver paste was developed using silver i-propylcarbamate ((CH3)2CHNHCOOAg) as the precursor of functional phase. The precursor had good solubility in water and methanol, high silver content (about 50 wt.%) and low decomposition temperature (below 200 °C). The paste was a non-Newtonian fluid with the viscosity depending significantly on the content of thickening agent (ethyl cellulose). When the paste was applied in micro-pen direct-writing process, it was able to produce high-resolution (20 μm or so) array patterns. After a homogeneous paste with about 40 wt.% silver i-propylcarbamate as the precursor was directly written and sintered at 180 °C for 15 min, an electrically conductive network consisting of more than 95 wt.% silver was formed and the network had a volume electrical resistivity in the order of magnitude of 10-5-10-6 Ω · cm and a sheet electrical resistivity in the order of magnitude of 10-4 Ω/square. View full abstract»

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  • Wafer-Level Vacuum Packaging of Micromachined Thermoelectric IR Sensors

    Page(s): 904 - 911
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1178 KB) |  | HTML iconHTML  

    In the trend towards low-cost, high-performance, and miniaturization, a wafer-level vacuum package is developed for micromachined thermoelectric infrared (IR) sensor. An IR sensor wafer and a cap wafer are bonded together in a vacuum chamber using Au-Au thermocompression bonding, where the cap wafer not only protects the floating thermopile structure but also selects IR light for the sensor. The device fabrication and Au-Au thermocompression hermetic bonding process as well as the packaged IR sensor characterization is presented in this paper. Experimental results show that the wafer-level vacuum packaged IR sensor has a four times higher responsivity and detectivity than the IR sensor with atmosphere pressure package, which confirms the IR performance improvement due to vacuum packaging. IR microscope image of the packaged device proved that the Au-Au thermocompression bonding process is compatible to the handling of fragile micromachined thermopile structure. Average leak rate and shear strength are, respectively, 3.9 × 10-9 atm cc/s and 16.709 Kgf, which shows that the Au-Au thermocompression hermetic bonding is suitable for the wafer-level vacuum packaging of micromachined thermoelectric IR sensor. View full abstract»

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  • Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging

    Page(s): 912 - 917
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1537 KB) |  | HTML iconHTML  

    Chip stacking with through-silicon-vias (TSV) technology for 3-D packaging of electronic devices was investigated. A new process of direct solder bumping on Si wafers without photoresist (PR) mould was designed and applied in this study. The Cu extrusion process on the via was also omitted for process simplification. This simplified process can be useful for cost reduction and increased productivity. The substrate for the experiments was a p-type 〈100 〉 Si wafer of 100 mm diameter. In order to produce the vias, the Si wafer was etched by a deep reactive ion etcher (DRIE) using SF6 and C4F8 plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO2, Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm2 and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm2 and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm2. The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by micro-soldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu6Sn5 intermetallic compound was pr- - oduced with a thickness of 3.2 μm. Through this study, a process for non-PR solder bumping by electroplating and wafer stacking with TSV was achieved successfully. View full abstract»

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  • Issues in the Use of Thermal Transients to Achieve Accurate Time-Constant Spectrums and Differential Structure Functions

    Page(s): 918 - 923
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    An analysis of accuracy of time-constant spectrum extraction from thermal transients has been performed. Numerical calculations based on analytical models and finite element method simulations have been used in order to obtain the thermal transients. Simple geometries have been used such that analytical expressions for their time-constant spectrums are known. Results show that a large error in the time-constant spectrum is obtained for very small rms error (<;1 mK) in the thermal transient. The estimation problem is ill-conditioned. Moreover, the differential structure function shows a low accuracy identifying stacked structures. The initial part of the differential structure function shows numerical oscillations and the final part has an asymptotic behavior to infinity that has been identified as an artifact related to errors in the time-constant spectrum estimation. Peak identification from the differential structure function heavily depends on an accurate determination of the time-constant spectrum. The limited spectral resolution and dynamic range of the differential structure function are a direct consequence of the time-constant spectrum imprecision. View full abstract»

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  • Transient Thermal Network Modeling Applied to Multiscale Systems. Part I: Definition and Validation

    Page(s): 924 - 937
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    This paper formulates the methodology of transient thermal network modeling (TTNM) for the study of unsteady heat transfer in systems where the presence of multiple length and time scales prevents the analysis by means of current computational or experimental techniques. The TTNM is based on reduced order models (ROMs) and it is established under the essential premise that a transient heat transfer process can be modeled by its division in a succession of stationary states and the division of the geometry in isothermal elements, according to the characteristic time and length scales obtained by scale analysis. The methodology is subsequently validated with canonical examples and considerations are given for the application to practical problems. View full abstract»

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  • Transient Thermal Network Modeling Applied to Multiscale Systems. Part II: Application to an Electronic Control Unit of an Automobile

    Page(s): 938 - 952
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    This paper applies the methodology of transient thermal network modelling (TTNM) introduced in Part I to the heat transfer analysis of an electronic control unit (ECU) located in the engine enclosure of a motorcar. The complexity of the geometry, the diverse heat transfer mechanisms involved and the duration of the operating cycle prevent the use of both simple, lumped models and detailed numerical simulations. The TTNM methodology relies instead in steady, approximate heat transfer correlations and a division of the system into the largest possible isothermal elements, based on the analysis of characteristic time and length scales. The dynamic heat balance of each element is then written down, conforming the TTNM of the system, which is numerically integrated with an adequate time step. The practical aspects of the TTNM methodology (design stage) are finally demonstrated; in this particular case-study, the model reveals a very high risk of damage of electronic components due to the radiative heat load received from the exhaust pipe of the engine. A design modification consisting of a radiative shield is proposed and model-tested, achieving an appropriate reduction of heat flux and temperatures, and thus an adequate protection of critical components. View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering