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ESSCIRC (ESSCIRC), 2011 Proceedings of the

Date 12-16 Sept. 2011

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Displaying Results 1 - 25 of 135
  • [Front matter]

    Page(s): i - viii
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    Freely Available from IEEE
  • ESSCIRC 2011 Table of contents

    Page(s): 1 - 35
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    Freely Available from IEEE
  • Analog design trends and challenges in 28 and 20nm CMOS technology

    Page(s): 1 - 4
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    Market trends for Multimedia Application Processor go on pushing CMOS technology in nanometer range. This puts analog design community in a strange paradox with simultaneously big challenges and tremendous opportunities. Analog is more than ever a key ingredient of advanced SoC with high performances PLL, giga samples high speed serial links and embedded power management. Challenge appears while achieving very high level of analog performances in a non analog-optimized and moving environment, inducing design architecture change and development of new design methodology. Opportunities come when analyzing nanometer MOS device performances which are going beyond analog designer dreams. These tremendous performances open the door for new sets of applications such as embedded mmW, digitally boosted analog functions with new market opportunities. The talk will highlight this new analog era coming with nanometer technologies. View full abstract»

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  • Circuit design in organic semiconductor technologies

    Page(s): 5 - 12
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    In this paper, we review the state of the art of digital and analog circuits that have been shown in recent years in organic thin-film transistor technology on flexible plastic foil. The transistors are developed for backplanes of displays, and therefore have the characteristics to be unipolar and to possess two gates. The dual-gate architecture is employed to increase the transistors intrinsic transconductance, and to create dual-VT logic. We highlight recent examples of digital and analog plastic thin-film circuits. Furthermore, we give an outlook into new technological evolutions, including thin-film semiconductors with high mobility, the advent of complementary thin-film circuits, and of thin-film electrically re-programmable nonvolatile memory. View full abstract»

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  • Photonics — Electronics integration on CMOS

    Page(s): 13 - 18
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    Silicon photonics has generated an outstanding interest for optical communications and for inter and intra-chip interconnects in electronic systems. High performance generic building blocks that can be used for a broad range of applications have already been demonstrated such as waveguides, I/O couplers, laser sources by III-V/Si heterogeneous integration, fast silicon modulators and germanium photodetectors. The paper will also review the different scenarios for integrating photonic functions with an electronic circuit, as well as the associated design, test and packaging challenges. View full abstract»

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  • Brain-machine interfaces as the new frontier in extreme miniaturization

    Page(s): 19 - 24
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    The exact functioning and operation of the brain has been and still is to a major degree a great mystery. The recent introduction of advanced imaging tools such as fMRI, EEG and eCoG and, most recently, direct neural sensing are throwing the doors of neuroscience wide open, and enable direct in-vivo observations of the brain at work in dynamic conditions. This may help to address a broad range of neural impairments and diseases, such as stroke, paralysis, epilepsy, depression, etc. However, for all of these to happen it is essential that neural interface circuitry is developed that surpasses the state of the art in ultra-low power miniaturized design by at least an order of magnitude. Furthermore, the resulting sensory/stimulation nodes have to be energy-self contained and support wireless links >; 1 Mbps. This paper explores the opportunities of accomplishing just that, and demonstrates the feasibility with a number of examples. The potential outcomes of these developments are just "mind-blowing", and can dramatically impact the evolution of human-cyber interfaces in the decades to come. View full abstract»

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  • Multimode-multiband transceivers for next generation of wireless communications

    Page(s): 25 - 36
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    Multi-standard connectivity has become de-facto for smart phones and laptops but is emerging also to other more specialized gadgets like e-book readers. Such devices need to be designed for the best performance even when multiple standards are operating simultaneously. In the future, RF band allocations will make the scene even more complex especially in LTE evolution towards band aggregation. Once RF transceiver architectures have evolved to be compliant with modern CMOS processes new challenges will rise to guarantee smooth user experience in high-speed applications independently of protocol or frequency band. This means stricter requirements in mutual interference and miniaturization from antenna to ASIC's. However, interplay between protocols may also open new opportunities to consider transceiver architecture options suitable for multi-standard radios. View full abstract»

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  • Wireless medical implant technology — Recent advances and future developments

    Page(s): 37 - 41
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    Wireless medical implant technology has been revolutionized in the last 10 years with the introduction of the world-wide Medical Implant Communication Service (MICS 402-405 MHz) and more recently MedRadio (401-406) MHz band. This has enabled the growth of remote monitoring with improved patient care. Recent advances and future developments in this growth area are presented. View full abstract»

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  • DC-DC converters: From discrete towards fully integrated CMOS

    Page(s): 42 - 49
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    Monolithic integration of electronic systems is one of the major techniques to reduce cost, size and power consumption in state-of-the-art consumer applications. Integration of transceivers and other mixed-signal building blocks has proven to be a very successful approach to build low cost, compact and portable systems [1]. Remarkably a certain building block remains discrete in commercial applications: the switched-power supply. This paper will demonstrate how recent research efforts cleared the path to develop fully integrated DC-DC converters in standard CMOS. View full abstract»

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  • High-k/metal gate innovations enabling continued CMOS scaling

    Page(s): 50 - 58
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    High-k dielectrics and metal gate electrodes have entered complementary metal-oxide-semiconductor (CMOS) logic technology, integrated in both gate-first and gate-last schemes. We review gate-first high-k / metal gate (HKMG) innovations enabling continued device scaling to the 22 and 14 nm nodes and beyond. First, we summarize some of the insight that allowed early HKMG challenges such as equivalent oxide thickness (EOT) and threshold voltage control to be overcome. Then, we discuss HKMG approaches that enable ultimate EOT scaling, pitch scaling via borderless source/drain contact formation, and the fabrication of multi-gate field-effect transistors. Finally, we summarize recent progress in gate stack development for high-mobility channel materials such as germanium and III-V compound semiconductors. View full abstract»

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  • Fundamentals and current status of steep-slope tunnel field-effect transistors

    Page(s): 59 - 60
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    The tunnel field-effect transistor (TFET) utilizes a metal-oxide-semiconductor MOS structure to control the Zener tunneling current in a p+n+ junction. Current understanding and status in the development of TFETs with steep inverse-subthreshold-slope is reviewed. View full abstract»

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  • Current status on GaN-based RF-power devices

    Page(s): 61 - 66
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    In this paper, we review the recent advances of GaN power switching and RF transistors developed at Panasonic. The presented devices are formed on cost effective Si substrates, which are very promising for the future mass production contributing to the reduction of the total fabrication cost. We develop the epitaxial growth technology using metal organic chemical vapor deposition (MOCVD) over 6-inch Si substrates by novel buffer layers relaxing the stress caused by the lattice and the thermal mismatches. Aiming at the power switching applications, we propose a new device structure called Gate Injection Transistor (GIT) for strongly desired normally-off operation together with low on-state resistances. The GITs are applied for an inverter to drive a motor which exhibits high operating efficiencies. Further increase of the breakdown voltages up to 2200V on Si is achieved by a novel Blocking Voltage Boosting (BVB) structure which prevents the inversion elections at the AlN/Si flowing at the periphery of the chips. As for the RF devices, we present 203W output power at 2.5GHz and 10.7W at 26.5GHz by AlGaN/GaN devices on Si. These GaN-based switching and RF power devices on Si substrates are very promising for a variety of applications taking advantages of their inherent low cost with superior performances. View full abstract»

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  • A 7-bit 18th order 9.6 GS/s FIR filter for high data rate 60-GHz wireless communications

    Page(s): 67 - 70
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    This paper presents the design and measurements of a 4× oversampled 18th order digital low-pass FIR filter aimed at replacing all analog baseband filters in a 60 GHz high data-rate wireless communication transmitter. Pipeline CPL adders and TSPC flip-flops are used to enable a very high output sample rate. The filter area is 0.1mm2 in a standard 65nm CMOS process. The interpolator has been designed to work at 10 GS/s. Measurements can be performed up-to 9.6 GHz on a 1.4V supply voltage and the filter consumes 400 mW. View full abstract»

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  • A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

    Page(s): 71 - 74
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    This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs. View full abstract»

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  • Area- and energy-efficient high-throughput LDPC decoders with low block latency

    Page(s): 75 - 78
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    The challenge in designing LDPC decoders is the efficient realization of the global communication between the two basic component types of such a decoder. Tight timing constraints in high-performance applications demand for a dedicated interconnect, which in general negatively affects the decoder features, especially the silicon area. Various approaches to reduce this impact have been discussed in literature which typically consider only a few if not just one level of the CMOS design process. However, for hardware efficient implementations a joint optimization on all design levels is mandatory. In this work we exemplarily present such an optimization for a (6, 32)-regular (2048, 1723) LDPC code ranging from an analysis of fix-point realizations of the decoding algorithm to an optimization on physical implementation level which can be applied to other codes, as well. The resulting decoder was implemented in a 40-nm CMOS technology. Circuit simulations of extracted netlists reveal an ATE-complexity reduction of more than one order of magnitude compared to known decoder implementations. View full abstract»

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  • A 2.56 Gb/s soft RS (255,239) decoder chip for optical communication systems

    Page(s): 79 - 82
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    Due to the increasing uncertainty of data for higher transmission rate, the Forward Error Correction (FEC) devices need to provide more powerful error correcting capability for optical communication systems. As compared with traditional hard RS decoders, the soft RS decoders can perform substantial coding gain but require much higher hardware complexity. In this paper, a decision-confined algorithm is proposed to enhance the error correcting performance with an area-efficient architecture. The novelty is that, instead of decoding numerous possible transmitted codewords and choosing the most likely one, only one candidate sequence will be decoded after confining the degree of error-locator polynomial Λ(x). For RS (255,239) codes, simulation results confirm that our approach provides 0.4 dB performance gain at 104 CER over the hard RS decoders. The experimental result reveals that our soft decoder can achieve 2.56 Gb/s throughput in standard CMOS 90 nm technology while having similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications. View full abstract»

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  • A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS

    Page(s): 83 - 86
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    A 128-entry × 128b content addressable memory (CAM) design enables 145ps search operation in 1.0V, 32nm high-k metal-gate CMOS technology. A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation. Scaling the supply voltage of the proposed CAM enables 0.3fJ/bit/search with 1.07ns search delay at 0.5V. View full abstract»

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  • A 3.4W digital-in class-D audio amplifier

    Page(s): 87 - 90
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    In this paper a class-D audio amplifier for mobile applications is presented realized in a 0.14μm CMOS technology tailored for mobile applications. The amplifier has a simple PDM-based digital interface that requires only two pins and enables assembly n 9-bump WL-CSP. A reconfigurable ate driver is used that reduces quiescent current consumption and radiated emission. View full abstract»

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  • An audio 91-dB THD third-order fully-differential class-D amplifier

    Page(s): 91 - 94
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    Class-D amplifiers exhibit high efficiency in spite of their simple implementation and, therefore, they are often used in portable devices with typical THD performance of the order of -65 dB. Presently, the possibility of using class-D amplifiers in applications requiring better THD (THD <; -85 dB) is being investigated, in consideration of their possible application in huge markets (like high-performance audio). For this reason, the THD performance of conventional class-D structures is not enough and new topologies have to be analyzed and implemented. In this paper, high-order class-D structures have been investigated to achieve the target THD performance. Among them, we selected a 3rd-order fully-differential class-D amplifier, which has been implemented in a 0.18-μm CMOS technology, starting from a previously available 1st-order class-D structure. The measurements on the realized 3rd-order device show a THD ≈ -91 dB with -1 dBFS input signal, about 30 dB better than the 1st-order structure. View full abstract»

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  • Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS

    Page(s): 95 - 98
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    Linearity and intrinsic gain enhancement techniques for realizing high-performance and low-voltage analog circuits in a deep-submicron CMOS are introduced. In place of a differential amplifier for the voltage-to-current (V/I) conversion at the input, a V/I conversion using a linear resistor and a positive feedback in a pseudo-differential configuration was adopted. The positive feedback concept was also applied to enhance the intrinsic gain of the deep-submicron MOS transistor which is used as a current source to realize high output impedance in amplifiers. In order to verify the effectiveness of the proposed techniques, a MOS 7th-order Gm-C linear phase low-pass-filter (LPF) was realized using a 65-nm CMOS process. Evaluation results showed that the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, less than -55 dB with a 100-MHz input and +10.3 dBm, respectively, all with a ±0.1 Vp-p signal input at each input terminal in pseudo differential configuration, while the LPF including an output buffer dissipated 60 mW from a 1.2-V supply. View full abstract»

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  • A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard

    Page(s): 99 - 102
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    This paper presents a fully differential 1.2V 8th-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SFDR, noise and selectivity, demonstrated by experimental measurements from a fabricated prototype. View full abstract»

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  • A 1.6mW 0.5GHz open-loop VGA with fast startup and offset calibration for UWB radios

    Page(s): 103 - 106
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    This paper presents a low-power fast-startup wideband VGA with a 6th-order low-pass filter function for UWB radios. A DC-coupled 6-stage open-loop topology is proposed, which includes DC offset calibration and fast-startup biasing circuits. The prototype in 90nm CMOS occupies only 0.075mm2, including decoupling capacitors and digital interfacing. The circuit consumes 1.6mW from a 1V supply, achieves -1.2dB up to 37.7dB gain with a programmable bandwidth from 80MHz to 460MHz, and achieves a startup-time of 12ns. View full abstract»

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  • A 100m-range 10-frame/s 340×96-pixel time-of-flight depth sensor in 0.18μm CMOS

    Page(s): 107 - 110
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    This paper introduces a high-performance optical depth sensor in a 0.18μm CMOS technology. At the core of the sensor, macro pixels consisting of 6×2 single-photon detectors enable accurate and selective time-of-flight measurements by taking advantage of temporal and spatial correlations of photons. An array of 32 high-throughput time-to-digital converters allows for the digitization of time-of-flight data with a resolution of 208ps within a range of 853ns, thus resolving distances up to 128 meters. Quantitative characterization of the chip sensor is reported. Depth map data acquired in a real-world situation illustrates the effectiveness of the approach in a road traffic environment. View full abstract»

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  • CMOS 3D image sensor based on pulse modulated time-of-flight principle and intrinsic lateral drift-field photodiode pixels

    Page(s): 111 - 114
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    Design and measurement results of a CMOS 128 × 96 pixel sensor are presented, which can be used for three-dimensional (3D) scene reconstruction applications based on indirect time-of-flight (ToF) principle enabled by pulse modulated active laser illumination. The 40μm pitch pixels are based on the novel intrinsic lateral drift-field photodiode (LDPD) that allows for a 30ns complete charge transfer from the photoactive area into the readout node, and accumulation of signal charge over several readout cycles for extended signal-to-noise ratio (SNR). Distance measurements have been performed using a specially developed camera system. View full abstract»

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  • A CMOS imager with digital phase readout for fluorescence lifetime imaging

    Page(s): 115 - 118
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    This paper presents a novel CMOS image sensor with direct digital phase output for fluorescence lifetime imaging applications. The phase-shift between intensity modulated excitation signal and emitted fluorescence is extracted utilizing a zero-crossing detection algorithm as a time-domain delay signal. A Time-to-Digital Converter (TDC) is subsequently used to quantize the time delay into digital output. A prototype sensor chip consisting of 32×32 passive pixel array, row-parallel phase extraction circuitry, and a global TDC is fabricated in 65nm low-power CMOS technology. The chip occupies 4mm×4mm silicon area with 1.2mW power consumption. Extensive characterization and phase image reconstruction results demonstrate both high sensitivity and good linearity performance of the digital phase readout. The TDC features 110ps temporal resolution over 414μs dynamic range. The proposed imager architecture offers an attractive solution for developing low-cost, low-power, and highly-integrated fluorescence lifetime imaging devices. View full abstract»

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