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Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date 7-10 Aug. 2011

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Displaying Results 1 - 25 of 429
  • [Front cover]

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    Freely Available from IEEE
  • Contents

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    Freely Available from IEEE
  • Phase-blender-based FIR noise filtering techniques for ΔΣ fractional-N PLL

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    This paper presents two FIR noise filtering techniques for ΔΣ fractional-N PLL, i.e. FIR-embedded PI and VCDL-based phase prediction. Without use of multiple CPs, PFDs and dividers, FIR-embedded PI realizes FIR noise filtering by averaging the output phases of interpolators. The FIR-embedded PI has been implemented in a 1 GHz ΔΣ fractional-N PLL and achieves the theoretically maximum bandwidth of 0.1×fref. The PLL, fabricated in a 0.13 μm CMOS, shows a reduction of phase noise by 34 dB. The VCDL-based phase prediction scheme also successfully performs the effective FIR filtering even without use of the multiple interpolators and provides a low power solution for FIR noise filtering in the design of ΔΣ fractional-N PLL. View full abstract»

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  • Wireline and wireless RF-Interconnect for next generation SoC systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    In the era of the nanometer CMOS technology, due to stringent system requirements in power, performance and other fundamental physical limitations (such as mechanical reliability, thermal constraints, overall system form factor, etc.), future SoC systems are relying more on ultra-high data rate scalable, re-configurable, highly compact and reliable interconnect fabric. To overcome such challenges, we explore the use of multiband wireline and wireless RF-Interconnect (RF-I) which can communicate simultaneously through multiple frequency bands with low power signal transmission, reconfigurable bandwidth and excellent mechanical flexibility and reliability. View full abstract»

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  • Design considerations for ADC-based backplane receivers

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    High-speed ADC-based backplane receivers often suffer from high power consumption and complexity and require careful designs. This paper discusses circuit- and system-level design considerations for such receivers. A low-power, high-speed front-end ADC circuit and a high-level design-space exploration of ADC-based receivers are presented. View full abstract»

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  • A 20Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter

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    Increasing data rates over electrical channels with significant frequency dependent loss is difficult due to excessive inter-symbol interference (ISI). In order to achieve sufficient link margins at high rates, I/O system designers implement equalization in the transmitters and are motivated to consider more spectrally-efficient modulation formats relative to the common PAM2 scheme, such as PAM4 and duobinary. This paper reviews when to consider PAM4 and duobinary formats, as the modulation scheme which yields the highest system margins at a given data rate is a function of the channel loss profile. A 20Gb/s triple-mode transmitter capable of efficiently implementing these three common modulation schemes and three-tap feed-forward equalization is presented. A power efficient quarter-rate duobinary precoder circuit is proposed which provides significant timing margin improvement relative to full-rate precoders. Simulation results in a 90nm CMOS technology compare the different modulation schemes over three backplane channels with different loss profiles. View full abstract»

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  • A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (690 KB) |  | HTML iconHTML  

    A highly energy-efficient on-chip communication network is crucial for the development of future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver was designed for the wireless Network-on-Chip (WiNoC) architecture. In order to reduce the power consumption of the transceiver, body-enabled circuit design techniques were implemented: Forward body-bias was used in the low-noise amplifier (LNA) and power amplifier (PA) circuits to lower the threshold voltages, reducing the supply voltage to 0.8 V. For up-and down-conversion mixers, power-hungry transconductance stages were eliminated by feeding the signals directly into the body terminals of the transistors. In addition, a novel feed-forward structure was designed to extend the bandwidth of the LNA at no cost in power consumption. Simulation results showed that the receiver has a double-sideband noise figure of less than 6 dB, and a peak gain of 20.5 dB, while the transmitter has an output P1dB of 0 dBm. The transceiver achieved an overall 3-dB bandwidth of 18 GHz. Compared with our previous design without body-enabled design techniques, the receiver power consumption was reduced by 20.3%. View full abstract»

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  • Multi-site on-chip current sensor for electromigration monitoring

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (947 KB) |  | HTML iconHTML  

    An on-chip current measurement method that is suitable for electromigration management is introduced. Rather than inserting a shunt in the current flow path for creating a voltage drop, the voltage drop across existing interconnects is used to determine the current flow. Current is measured with a MOSFET-only sensing circuit that provides 9 bits of resolution with midrange current levels at the threshold where electromigration concerns become relevant. This current sensor can be used for sensing currents in either VDD or VSS busses and is targeted for use in the power power/thermal management units in integrated circuits. Simulation results show the DNL/INL of this sensor is within +0.15/-0.3 LSB. The current sensor is robust to local mismatch. The small area and low power dissipation makes the structure suitable for multiple-site on-chip current measurements. View full abstract»

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  • A 0.6V 200kHz silicon oscillator with temperature compensation for wireless sensing applications

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    This paper presents a silicon oscillator suitable for low-cost and low-power wireless sensing applications. With the comparisons of ring oscillators in different temperature coefficients, the frequency of an internal ring oscillator is estimated and parameterized by a second-order polynomial. Accordingly, the output clock is compensated in a frequency division fashion. The oscillator is implemented in 90-nm CMOS technology with an area of 0.04mm2. Operating at 0.6V, the output frequency is within 200±1kHz over the temperature range of Ȓ25°C to 125°C with power consumption of 48μW. View full abstract»

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  • High speed CMOS vision chips

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1073 KB) |  | HTML iconHTML  

    This paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N×N) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the 0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated. View full abstract»

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  • Differential capacitance-to-digital converter utilizing time-domain manipulation of intermediate signals

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (911 KB) |  | HTML iconHTML  

    To achieve high-resolution in electrically noisy environments as well as low-power, we propose a differential capacitance-to-digital converter (CDC) that utilizes three-level time-domain manipulation of intermediate signals. The proposed CDC, designed in 0.35 μm digital CMOS technology and simulated with HSPICE, achieves a 9-bit resolution at the power supply of 3.3 V with the superimposition of 600 mVpp 2.5 kHz square-wave noise disturbance, consuming the average power of 158.3 μW/sample. View full abstract»

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  • A 5.3 µW contact monitoring sensor with BCC electrode and MICS antenna for energy efficient unified WBAN transceiver

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1168 KB) |  | HTML iconHTML  

    A low power contact monitoring sensor for an energy efficient implantable and wearable wireless body-area-network (WBAN) transceiver is implemented in 0.18 μm CMOS process. The transceiver utilizes 30 - 70 MHz for the body channel communication (BCC) and 402 - 405 MHz for the medical implant communication service (MICS) with a pattern-printed electrode interface for operating as both BCC electrode and MICS antenna. The contact monitoring sensor adopts the reflection wave detection technique to compensate for the channel quality degradation due to the variation of the contact distance between the electrode and the human body. The reflection wave detection is achieved by an energy efficient envelope detector and a 2-bit ADC with a programmable reference voltage. It leads to mitigate both the linearity and sensitivity requirements of the receiver front-end by more than 10 dB. As a result, with the power consumption of 5.3 μW, the proposed contact monitoring sensor reduces the power consumption of the LNA more than 70%. View full abstract»

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  • Reuse of flexible hardware modules for practical implementation of intra H.264/SVC video encoder

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB) |  | HTML iconHTML  

    The practical implementation of a scalable video encoder requires for very high processing demands. In particular, the H.264/SVC is an emergent standard which combines distinct complex techniques in order to remove redundant data among consecutive layers, impacting in the global encoder complexity increasing. In order to evaluate that, this paper presents a detailed analysis of the required demands of a practical H.264/SVC video encoder. Considering these demands, it is proposed here an innovative approach, which uses flexible computational hardware modules in order to perform iteratively the SVC intra computational coding, for both the base layer and enhancement layers. The proposed solution was implemented in VHDL and compared with other conventional hardware approaches, confirming significant memory and used chip area savings. The aim of this proposal is to contribute to the research community with an innovative and practical solution for the development of scalable video encoders. View full abstract»

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  • Low bandwidth fractional motion estimation in H.264 design for mobile devices

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (733 KB) |  | HTML iconHTML  

    The conventional fractional motion estimation(FME) approach needs a two-step interpolation for half-pel and quarter-pel refinements. Though two-sequential-step brings high encoding performance, it introduces a huge computational load and memory bandwidth requirement for searching seventeen fractional points for each of the forty-one motion vectors. These obstacles become more difficult when running the applications on mobile device with the limitation of power and hardware resource. In this paper, a low bandwidth FME design is proposed with two techniques. Based on high correlation between motion vector of a block and its up-layer as well as relationship of integer candidates, one-step FME algorithm is proposed to reduce computation complexity and memory bandwidth requirement. In addition, a memory saving scheme is proposed while carefully considering the trade-off between hardware resource and memory saving. Experimental results show that the proposed design just needs 66% of gate counts and saves 88% of memory bandwidth when compared with previous design. View full abstract»

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  • Power-rate-distortion modeling for energy minimization of portable video encoding devices

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1053 KB) |  | HTML iconHTML  

    In portable multimedia devices, one of the most critical issues is to minimize the energy consumption and thereby prolong the operational lifetime of the system while maintaining the required video quality. In this paper, we proposed a power-rate-distortion (P-R-D) model of video encoding system to maximize its lifetime. The proposed P-R-D model of video encoder is generated in two steps. The first step is the modeling process of the relationship between the power consumption and the distortion of video encoder. For this, we developed a power consumption model of a video encoder based on a power-scalable architecture of H.264/AVC encoder using the power consumption data of each functional module. The second step is generating the unified P-R-D model based on the P-D model and the conventional rate-distortion (R-D) model. Experimental results show that the proposed P-R-D model describes the relationship among power, rate, and distortion with 0.99 of the R-square value on the average. View full abstract»

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  • Prediction mode reordering and IDCT direction control for fast intra 8×8 prediction

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (969 KB) |  | HTML iconHTML  

    This paper presents a novel architecture of intra 8×8 prediction for a high profile H.264 intra frame encoder. Intra 8×8 prediction consists of prediction and reconstruction phases and two phases are performed in a pipeline manner. In the 2-stage pipelined schedule, bubbles between prediction and reconstruction phases are the main bottleneck for fast 8×8 prediction. To reduce bubbles, prediction mode reordering and Inverse Discrete Cosine Transform (IDCT) direction control schemes are proposed. The proposed schemes reduce 115 cycles of bubbles to perform intra 8×8 prediction for a macroblock and achieve a 24.5% speed-up. View full abstract»

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  • Efficient rate-distortion optimized mode selection of H.264/AVC intra coding

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (529 KB) |  | HTML iconHTML  

    Rate-distortion optimization (RDO) can significantly improves encoder performance in H.264-like video coding applications. In H.264/AVC, rate-distortion optimization (RDO) method has to code the video by exhaustively trying all the mode combinations including the different intra- and inter-prediction modes. Therefore, the complexity and computation load of video coding in H.264/AVC increase drastically compared to any previous standards. This paper reviewed the conventional fast cost functions of the intra encoder and proposed an enhanced low complex cost function for H.264/AVC intra 4×4 mode selections. The enhanced cost function uses sum of absolute Hadamard-transformed differences (SATD) and mean absolute deviation of the residual block to estimate distortion part of the cost function. A threshold based large coefficients count is also used for estimating the bit-rate part. The proposed method improves the rate-distortion performance of the conventional fast cost functions while maintaining low complexity requirement. As the results, the encoding process can be significantly accelerated with use of the proposed cost function. Simulation results confirmed that the proposed method reduced about 85% of computation of original encoder with negligible rate-distortion performance degradation. View full abstract»

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  • Equalization of non-linear channels using a Volterra-based non-linear adaptive filter

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    In order to achieve higher data throughput on fixed-bandwidth satellite non-linear channels, using higher-order modulations, we propose the use of a Volterra-model based nonlinear channel equalizer. Typically, a travelling wave tube (TWT) amplifier or a solid-state power amplifier (SSPA) is used in the satellite nonlinear channels. For higher than 4-QAM schemes, the nonlinear characteristics of the power amplifier stage in the transmitter typically introduce significant amplitude and phase distortions to the transmitted signal. We also propose the use of lower-order Volterra-series based adaptive filters for this application especially if rectangular-pulse shaping is used. This enables us to speed up the convergence time of the algorithm. Simulations results using 16-QAM and 32-QAM are presented to support the claims. View full abstract»

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  • The effect of HPA non-linearity on the repeater signal with feedback and combined compensation

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    Cancellation of echoes in mobile communication systems using repeaters and satellites is an on-going research issue. We show that the echoes in the repeaters can be eliminated if the non-linearity of HPA (High Power Amplifier) at the re-transmitter is compensated. We propose an echo cancellation using the indirect learning architecture (ILA) along with the pre-distorter for the HPA. We verify the performance of the proposed echo cancellation through computer simulation. View full abstract»

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  • Complex adaptive notch filter for detection of real sinusoid

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    This paper presents a new realization of adaptive notch filter based on a cascade of complex first-order notch filters. Unbiased frequency estimation of a real sinusoid has been achieved by thinning the notch bandwidth. It has been shown that the simple closed form of mean square error (MSE) for frequency estimation is given by using the results for first-order complex notch filter and its robustness to the frequency of input sinusoid has been shown. Computer simulation results are presented to validate the analysis. View full abstract»

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  • Low complexity adaptation for channel shortening equalizers

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    Since the days of Digital Subscriber Links(DSL), Time Domain Equalizers(TEQ's) have been used to combat time dispersive channels in Multicarrier Systems. In this paper, we propose computationally inexpensive techniques to recompute TEQ weights in the presence of changes in the channel, especially over fast fading channels. The techniques use no extra information except the perturbation itself, and provide excellent approximations to the new TEQ weights. The proposed adaptation techniques are shown to perform admirably well for small changes in channels for OFDM systems. View full abstract»

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  • A 2D IIR spatially-bandpass antenna beamformer on a 65 nm Achronix SPD60 asynchronous FPGA

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1009 KB) |  | HTML iconHTML  

    An asynchronous implementation of spatially-bandpass 2D IIR frequency-planar digital filter is investigated for obtaining high-speed and low-power digital filter circuits compared to the synchronous implementations. The reduced power consumption and higher speed of operation of the asynchronous architecture has emerging applications in radio-astronomy, space science, radar, and wireless communications. The direct-form-I realization of a 2nd-order spatially-bandpass 2D IIR filter is extended to a clock-free asynchronous implementation using asynchronous FPGAs from Achronix Semiconductor. The experimental results presented here show that the speed of operation of the asynchronous implementation of the spatially-bandpass 2D IIR filter, in direct-form-I, is 31% higher than its synchronous counterpart, for a look-ahead of 4th-order. View full abstract»

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  • Emerging non-volatile memory technologies for reconfigurable architectures

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    This work evaluates the potential application of emerging non-volatile memory technologies to reconfigurable architectures based on hybrid CMOS/resistive-switching FPGAs. The non-volatility of these devices lends them well to designs requiring low power consumption and reduced configuration time at power up. These memory technologies are assessed based on their effectiveness for use as interconnect routing switches in terms of programming power, reliability, scalability, and fabrication cost. The feasibility of architectural integration and innovations in reconfigurable architecture for non-volatile memories are also discussed. With sufficient redundancy and defect-tolerance, hybrid FPGA architectures may facilitate the integration of emerging non-volatile memory technologies with reconfigurable logic. View full abstract»

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  • Techniques for improving coarse-grained reconfigurable architectures

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    This paper presents various novel techniques for improving coarse-grained reconfigurable architectures. Specifically, it presents techniques for supporting IEEE single precision floating-point standard, efficient handling of loop-carried dependency with variable-length FIFOs, efficient mapping of control flows, and sharing data with a host processor for transparent binary acceleration. Experiments with benchmark examples demonstrate the effectiveness of the proposed techniques. View full abstract»

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  • Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

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    This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches “contexts” consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples. View full abstract»

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