Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

2-4 Dec. 1998

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  • Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

    Publication Year: 1998
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    Freely Available from IEEE
  • Testing Embedded Memories: Is BIST The Ultimate Solution? Answers to the Key Issues

    Publication Year: 1998, Page(s):520 - 525
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    First Page of the Article
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  • Author index

    Publication Year: 1998, Page(s):526 - 528
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    Freely Available from IEEE
  • A DFT methodology for high-speed MCM based on boundary scan techniques

    Publication Year: 1998, Page(s):521 - 525
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  • "The new frontier for testing: nanometer technologies"

    Publication Year: 1998, Page(s):2 - 6
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    The onset of deep sub-micron (now currently alluded to as nanometer technology) is changing the way chips are being designed and manufactured. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality. Test is one part of this process that is getting significant attention. An area once classified as ... View full abstract»

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  • A BIST structure to test delay faults in a scan environment

    Publication Year: 1998, Page(s):435 - 439
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB)

    When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the serial s... View full abstract»

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  • Complete search in test generation for industrial circuits with improved bus-conflict detection

    Publication Year: 1998, Page(s):212 - 219
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Test Pattern Generation (TPG) for sequential and/or 3-state circuits involves two important aspects which often are handled incorrectly: bus conflict detection and completeness of search in TPG. The correct handling of both aspects strongly depends on the signal model used by TPG. We propose a novel, set-based, signal model using the power-set (i.e., the set of all possible subsets) of the basic v... View full abstract»

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  • Evaluating BIST architectures for low power

    Publication Year: 1998, Page(s):430 - 434
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    The “system-on-chip” revolution has posed a number of new challenges to the test engineers. We address the issue of high power dissipation during testing, which can reach levels that are beyond the safe upper limit associated with the chosen packaging technology. A study undertaken by Zorian (1993) reveals that test power can be as large as 200% or more in comparison to the normal powe... View full abstract»

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  • An approach to the on-line testing of operational amplifiers

    Publication Year: 1998, Page(s):290 - 295
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    A new approach for the on-line testing of operational amplifiers embedded into analog and mixed-signal circuits is presented in this paper. A built-in detector is used for providing an on-line test signal, which is suitable for concurrent error detection in operational amplifiers. The fault detection strategy is based on monitoring via an analog checker the normal output/input and the on-line sign... View full abstract»

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  • Dynamic power supply current testing of CMOS SRAMs

    Publication Year: 1998, Page(s):348 - 353
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    We describe the design and implementation of a dynamic power supply current sensor which is used to detect SRAM-specific faults such as disturb faults as well as logic cell faults. The sensor detects disturb faults by detecting abnormal levels of the power supply current. The sensor is embedded in the SRAM and offers on-chip detectability of faults View full abstract»

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  • A non-scan DFT method for controllers to achieve complete fault efficiency

    Publication Year: 1998, Page(s):204 - 211
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test appl... View full abstract»

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  • Exploiting BIST approach for two-pattern testing

    Publication Year: 1998, Page(s):424 - 429
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Detection of delay and transistor stuck-open faults requires two-pattern tests. BIST provides a low-cost test solution. This paper exploits the BIST approach for two-pattern testing. The generation of a pseudo-deterministic test-pair sequence with LFSR was exploited. A three-step approach is proposed. First, a set of deterministic test-pair is generated to detect all robust path delay faults. Seco... View full abstract»

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  • A probabilistic model for path delay faults

    Publication Year: 1998, Page(s):70 - 75
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we enter the deep submicron age. However, it is difficult in general, since the number of faults normally is very large and most faults are hard to sensitize. To make delay fault testing and test synthesis easier, we propose a probabilistic PDF model. We investigate probability density functions for wire and path d... View full abstract»

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  • Analog module metrology using MNABST-1 P1149.4 test chip

    Publication Year: 1998, Page(s):378 - 382
    Cited by:  Papers (2)
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    This paper presents a metrology to extend P1149.4 from external component testing to internal module measurement. A series of experiment has been conducted to verify that the metrology is able to tolerate parasitic effects and test signal variation. As compare to the direct measurement, the metrology achieves an improvement of 14 dB in measurement SNR. Furthermore, it also extends the frequency ra... View full abstract»

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  • Testing and diagnosis of interconnect structures in FPGAs

    Publication Year: 1998, Page(s):283 - 287
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    Since Field Programmable Gate Arrays (FPGAs) are reprogrammable, faults in them can be easily tolerated once fault sites are located. Previous research on diagnosis of FPGAs mainly deal with faulty logic blocks. In this paper we present a method for the testing and diagnosis of faults in the interconnect structures of FPGAs. A predefined set of tests that can locate all single faults and many mult... View full abstract»

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  • Partitioning and reordering techniques for static test sequence compaction of sequential circuits

    Publication Year: 1998, Page(s):452 - 457
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vecto... View full abstract»

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  • False-path removal using delay fault simulation

    Publication Year: 1998, Page(s):82 - 87
    Cited by:  Papers (3)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All links of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a nonenumerative pat... View full abstract»

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  • Formal design techniques-theory and engineering reality

    Publication Year: 1998, Page(s):394 - 398
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    The explosion in the complexity of today's chips is rapidly pushing the traditional simulation based verification approach to its limits. This paper examines formal verification techniques as solutions to this problem. The term is used for mathematically rigorous design checking from formal proof processes to relatively computationally `easy' structural equivalence checking. It is argued that ther... View full abstract»

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  • Consequences of port restrictions on testing address decoder faults in two-port memories

    Publication Year: 1998, Page(s):340 - 347
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only... View full abstract»

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  • Static test compaction for scan-based designs to reduce test application time

    Publication Year: 1998, Page(s):198 - 203
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. For every subsequence, it also accepts the vector to be scanned-in before the subsequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines tes... View full abstract»

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  • A ring architecture strategy for BIST test pattern generation

    Publication Year: 1998, Page(s):418 - 423
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1156 KB)

    This paper presents a new effective BIST scheme that achieves 100% fault coverage with low hardware overhead, and without any mollification of the circuit under test, i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator (e.g. an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring ... View full abstract»

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  • Integrated current sensing device for micro IDDQ test

    Publication Year: 1998, Page(s):323 - 326
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    A current sensing device, namely a Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement, which can be used for IDDQ testing of internal circuit blocks. The HEMOS can be manufactured and integrated in a VLSI device with the conventional CMOS process. The HEMOS is also helpful in establishing the low standb... View full abstract»

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  • BISTing switched-current circuits

    Publication Year: 1998, Page(s):372 - 377
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits one to ... View full abstract»

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  • Test cycle count reduction in a parallel scan BIST environment

    Publication Year: 1998, Page(s):21 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based built-in-self-test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of appl... View full abstract»

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  • Fast window test method of hysteresis test

    Publication Year: 1998, Page(s):179 - 183
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    The conventional method of hysteresis test for digital input pin, as defined by (Vih-Vil), performs two VLS (Voltage Level Search) to measure the actual Vih and Vil. A typical tester spends an average of 120 ms for each VLS, resulting in a test time of 240 ms for each pin requiring a hysteresis test. This paper introduces a new method which is 70 times faster than the conventional method. The pres... View full abstract»

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