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Ph.D. Research in Microelectronics and Electronics (PRIME), 2011 7th Conference on

Date 3-7 July 2011

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  • [Front cover]

    Page(s): c1
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  • [Title page]

    Page(s): I
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  • [Copyright notice]

    Page(s): II
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  • Foreword

    Page(s): III
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    It is our great pleasure to welcome you to Italy to the 7th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2011), jointly organized by the Smart Optical Sensors and Interfaces research unit of Fondazione Bruno Kessler and the Department of Information Engineering and Computer Science of the University of Trento. View full abstract»

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  • Conference committees

    Page(s): V - VI
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  • Table of contents

    Page(s): VII - XIII
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  • Multi-radio integration into scaled CMOS SoCs

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4704 KB) |  | HTML iconHTML  

    The trend of merging computation and wireless communications into SoCs has its reflection on the underlying circuits. Integrating multiple radios into an advanced CMOS process has the potential to reduce costs, ease platform integration and enable further area scaling over technology nodes. This is the case, however, only if the radios are designed with a completely new mindset: Focusing on “digital CMOS-friendly” implementations, robust against interference and process variation. Radio architectures have to be reconsidered to enhance their linearity, while reducing analog and RF complexity where possible. Process scaling lowers the cost of digital signal processing, which can be exploited for digitally assisted analog, Build-In-Self-Test (BIST) and calibration, leading to small, scalable, reliable and low power CMOS radios. View full abstract»

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  • An FPGA based diagnostic tool for jitter optimization in serial high-speed transceivers

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    We present an embedded jitter measurement system for on-chip diagnostics of serial high-speed interfaces. A Virtex-5 FPGA uses a 3Gbit reference signal to retrieve timing jitter distributions from a system under test (SUT). Using a recently developed fitting method, the total jitter of the system is determined, which allows for judging the quality of transmission lines, PLLs or transceiver structures. The diagnostic tool is thus able to optimize and configure the SUT without the use of an additional instrumentation device. View full abstract»

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  • Filter partitioning optimum strategy in homodyne multi-standard radio receivers

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    This paper analyzes the filter partitioning in the channel selection of direct conversion multi-standard radio receivers. The paper develops a systematic design methodology for optimum filter partitioning between the multi-standard receiver baseband analog Low Pass Filter (LPF) and the digital filter following the A/D conversion. To this aim, a new and efficient tool is introduced: the generic blockers diagram. Subsequently, a Figure of Merit (FOM) is defined to assess the trade-off between the analog LPF area and ADC power consumption. Thus, the designer is enabled to handle efficiently the large amount of information provided in the envisaged wireless standards. The first order, system level, analysis method based on the new generic blockers diagram, presented in this paper, is an efficient design tool for partitioning the multi-standard receiver block specifications. View full abstract»

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  • Simulation environment for blocker detection in LTE systems

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    In the recent past several approaches about energy efficient user equipments (UE) using intelligent analog and digital frontends (AFE/DFE) have been discussed. Those, which will be referred to in this paper, face the fact, that although efficient energy budget management is an important issue in mobile communication systems, typically quite an amount of energy is wasted in todays UEs. The reason for this is, that both AFEs and DFEs in communication systems are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. In a real receiving process those requirements can typically be considered as dramatically less critical. Capturing the environmental transmission conditions and adapting the receiver architecture to the actual needs allows to save energy during the receiving process. In order to face this problem and provide solutions to the given issue, a flexible simulation environment (SE) has been implemented using Matlab. This SE focuses on the Long Term Evolution test case, but is not limited to it. In this paper the structure and configuration abilities of the implemented SE will be described. References to simulation results achieved by using the system will be provided to demonstrate the possibilities of the given architecture. View full abstract»

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  • Observations on the resolution and tones in First Order Noise Shaping Time-to-Digital Converters

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (547 KB) |  | HTML iconHTML  

    In this paper we report some observations on the resolution and tones of First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converters (LO TDCs). We describe the architecture and governing equations of the LO TDC. We introduce equations to predict the resolution of the system “LO TDC plus moving average filter” and the frequency and amplitude of the largest amplitude tone in the spectrum of the TDC output when the input is constant. We describe briefly the block diagrams of a Matlab model of the LO TDC and its implementation on an FPGA. Finally, we compare analytical predictions of the amplitude and frequency of the largest tone in the spectrum with simulations and experimental results. The prediction of the powers and positions of the tones in the TDC output spectrum is fundamental for the design of the system in which the TDC has to be used. View full abstract»

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  • Monolithic Time-to-Amplitude converter for TCSPC applications with 45 ps time resolution

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (555 KB) |  | HTML iconHTML  

    In recent years many applications exploiting the measurement technique of time-correlated single photon counting (TCSPC), that allows the analysis of extremely fast and weak light waveforms with a picoseconds resolution, have been developed in several fields such as medicine and chemistry. Moreover, the development of single photon avalanche diode arrays and of multianode PMT led to the realization of acquisition systems with several parallel channels to employ the TCSPC technique in even more applications. One of the most important sections of a TCSPC acquisition chain is the time measurement block, which must present high resolution and low differential nonlinearity, and in order to realize multidimensional systems, it has to be integrated to reduce both cost and area. In this paper we present a fully integrated Time-to-Amplitude converter (TAC), built in 0.35 μm Si-Ge technology, characterized by a very good time resolution (45 ps), low differential nonlinearity (better than 4% peak to peak and 0.2% rms), high counting rate (16 MHz), low and constant power dissipation (less than 50 mW), and low area occupation (1.38×1.28 mm2). View full abstract»

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  • 15bit Time-to-Digital Converters with 0.9% DNLrms and 160ns FSR for single-photon imagers

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1642 KB) |  | HTML iconHTML  

    We present a high precision Time-to-Digital Converter (TDC) architecture suitable for multi-channel implementations in monolithic arrays of single-photon avalanche diode (SPAD) detectors aimed at TCSPC applications (like FLIM, FCS, FRET), but also at photon timing and direct TOF measurements for 3D ranging applications (e.g. in LIDAR systems). A “smart-pixel” with a SPAD detector, an analog sensing and driving electronics and a TDC is able to detect single photons and to measure and record in-pixel the time delay between a START pulse (e.g., laser excitation, cell stimulus, or LIDAR flash) and a STOP pulse given by the detection of a single photon (e. g., fluorescence decay signal or back reflection from an object). We report on the design and characterization of prototype chips, fabricated in a 0.35 μm standard CMOS technology. With a 100 MHz reference clock, the TDC provides a time-resolution of 10 ps, a dynamic range of 160 ns and DNL <;1 % LSB rms. View full abstract»

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  • FoM to compare the effect of ASK based communications on remotely powered systems

    Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB) |  | HTML iconHTML  

    This paper presents a Figure-of-Merit to compare the remotely powered communication systems. The important parameters for remote powering and also communication are presented. The effect of ASK based communications on remote powering performance is analyzed by representing the challenges of power transfer during data transmission. This Figure-of-Merit is introduced to compare different modulation types in terms of powering and communication performances. View full abstract»

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  • FlexDEF: Development framework for processor architecture implementation and evaluation

    Page(s): 37 - 40
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    Designing a processor is a complex task that uses multiple and varied tools. The complete development cycle spans software as well as hardware design and verification. More often than not, in spite of the close dependencies between hardware and software, there is no common platform for quick and accurate testing of these dependencies. Though such systems are often employed in industry, it is not common for end-to-end frameworks to be deployed in educational and research settings. We present the FlexCore Design Exploration Framework (FlexDEF), an end-to-end tool-chain used to develop the FlexCore processor and its accompanying cache system. The tool-chain is a hierarchically linked system that spans the various development phases involved in design and verification. The processor system is intended to be a model, for use in research-oriented projects where both the software and hardware are in a constant state of flux. We discuss the complete framework and the advantages in each context. Finally, we summarize the developments and discuss the future of the FlexDEF tool-chain. View full abstract»

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  • Power gating multiplier of embedded processor datapath

    Page(s): 41 - 44
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    Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the embedded architecture of FlexCore, to evaluate if leakage reductions in temporarily idle units can reduce the overall power dissipation of compute-intensive applications. Post-layout multi-corner simulations for a 65-nm FlexCore datapath implementation demonstrate that power gating of the multiplier unit yields overall datapath energy savings, up to 14%, for two EEMBC benchmarks. View full abstract»

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  • A 19MFLIPS CMOS fuzzy controller to control continuously variable transmission ratio

    Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (550 KB) |  | HTML iconHTML  

    Implementation of a new fuzzy logic controller in CMOS technology which enhances the control speed and precision of continuously variable transmissions in automobile is presented in this paper. The maximum delay for the proposed fuzzy logic controller is 52 ns that corresponds to 19.23MFLIPS. Mixed analog/digital realization of the circuits makes the controller programmable to various types of companies and automobiles. Simulation results of the controller using HSPICE and level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology, demonstrate a power consumption of 6.7 mW, and 2.02% RMS error of output surface compared to ideal results obtained from MATLAB. View full abstract»

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  • Handheld bio-impedance measurement system based on an instrument-on-chip

    Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    In this paper we present a compact system for impedance measurement in the kHz-MHz frequency range with attoFarad resolution. It has been designed to address micro- and nano-scale bio-sensing applications, such as impedimetric flow cytometry or molecular affinity bio-sensors. The core of the detection system is an integrated circuit that features a low noise current amplifier, a two-phase square waveform lock-in detector and two ΣΔ analog-to-digital converters. The CMOS chip is complemented by all the blocks needed to perform spectroscopy measurements, including versatile signal generation, digital processing and PC data transmission. The whole stand-alone system is USB powered and can reach sub-fF resolution in capacitive tracking on a sub-millisecond time scale. View full abstract»

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  • Design of an electronic oscillator for biosensing applications based on a MEMS resonator

    Page(s): 53 - 56
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    Resonant mass sensors (i.e. microbalances) are commonly used in chemical and biochemical sensing, and their MEMS counterparts, based on MEMS resonators, are actively investigated. In this work, we present the design of an integrated electronic oscillator, based on general purpose CMOS operational amplifiers (op-amps) and conceived to operate with a magnetically actuated MEMS resonator fabricated on the same chip as the op-amps. After a description of the resonator and op-amp structure and characteristics, a two-stage, positive feedback oscillator topology is presented. The simulated behavior of the oscillator is presented and discussed, and the temperature stability of the oscillator output frequency is analyzed. View full abstract»

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  • Electrochemical impedance spectroscopy study of the cells adhesion over microelectrodes array

    Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB) |  | HTML iconHTML  

    Electrochemical Impedance Spectroscopy (EIS) has been widely used in biological studies like tissue and cells characterization, both in vivo and in vitro. The objective of this study was to investigate cells adhesion over a microelectrodes array by monitoring the electrical impedance. A comprehensive electrical model of the cell-electrode interface has been used to fit experimental data. The electrode surface coverage has been evaluated both with the variation of impedance measurements and with the variation of parameters extracted from the electrical model. A cover factor β has been used in the model in order to quantify the presence of different number of cells over an electrode surface. View full abstract»

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  • Design of a cantilever-based system for DNA detection

    Page(s): 61 - 64
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    In this work we present the development of a system intended for DNA label free detection, based on piezoresistive microcantilever arrays and dedicated readout ASIC. Detector design and microfabrication technologies have been optimised for detection sensitivity, providing an efficient direct electrical measurement of DNA hybridisation. Readout ASIC has been implemented using a 0.35μm CMOS technology to provide a high resolution and low noise readout of the sensors, by also providing the compensation of large offset in the detector response. View full abstract»

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  • A CMOS equalizer for short-reach optical communications

    Page(s): 65 - 68
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    This paper presents a new CMOS analog equalizer for short-reach optical communications with tuning range between 300 MHz and 3.6 GHz. The prototype has been designed in a standard 0.18 μm CMOS process. This equalizer uses a current-mode process to decrease the supply voltage and the power consumption. Thus, it operates with a supply voltage of 1 V and has a power consumption of 1.1 mW. View full abstract»

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  • Operational amplifier design for high-speed pipelined Analog-to-Digital Converters in deep-submicron CMOS processes

    Page(s): 69 - 72
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    In this paper, design challenges of an operational amplifier (opamp) for medium-resolution pipelined Analog-to-Digital Converters (ADCs) in deep-submicron CMOS processes are discussed. Comparisons are made between basic opamp topologies in 130 nm CMOS process, concerning particularly on gain, bandwidth, signal headroom and power consumption with 1.2V supply. View full abstract»

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  • High precision injection circuit for in-pixel calibration of a large sensor matrix

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    This work will discuss the design of a high linearity, low dispersion injection circuit to be used for pixel-level calibration of detector readout electronics. In hybrid pixel detectors, the circuit provides a useful means for precise analog test of the pixel cell unit already at the chip level, when no sensor is connected or the detector has been connected to the chip. Moreover, it provides a simple means for calibration of readout electronics in monolithic active pixel sensors. Two injection techniques were investigated in this paper, one for charge and one for transresistance readout architecture. The aim of the paper is to discuss the design guidelines for the calibration circuit and to present the relevant simulation results of the system, which has been implemented in a 130 nm CMOS technology. View full abstract»

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  • Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology

    Page(s): 77 - 80
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    This work is concerned with the design of two different analog channels for hybrid and monolithic pixels in view of applications to the vertex detector at the SuperB Factory. The circuits have been designed in a 130 nm CMOS, vertical integration technology, which may provide some advantages in terms of functional density and electrical isolation between the analog and the digital section of the front-end. The paper discusses the main features of the two channels, with emphasis on some specific problems and their solution through purposely devised blocks and suitable design criteria. View full abstract»

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