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2011 Sixteenth IEEE European Test Symposium

23-27 May 2011

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Displaying Results 1 - 25 of 65
  • [Front cover]

    Publication Year: 2011, Page(s): C1
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  • [Title page i]

    Publication Year: 2011, Page(s): i
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  • [Title page iii]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - ix
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  • Foreword

    Publication Year: 2011, Page(s): x
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  • Organizing Committee

    Publication Year: 2011, Page(s):xi - xii
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  • Steering and Program Committee

    Publication Year: 2011, Page(s): xiii
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  • Best Paper Award

    Publication Year: 2011, Page(s): xiv
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  • Test Technology Technical Council

    Publication Year: 2011, Page(s):xv - xvii
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  • Plenary Presentation Keynotes

    Publication Year: 2011, Page(s):xviii - xix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Diagnosis of Failing Scan Cells through Orthogonal Response Compaction

    Publication Year: 2011, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB) | HTML iconHTML

    This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal- spatial and time- signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compactio... View full abstract»

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  • Improved DFT for Testing Power Switches

    Publication Year: 2011, Page(s):7 - 12
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off,... View full abstract»

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  • Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches

    Publication Year: 2011, Page(s):13 - 18
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    Power-gating structures for intermediate power-off modes offer significant power saving benefits as they reduce the leakage power during short periods of inactivity. However, reliable operation of such devices must be ensured by using adequate test methods. We propose a signature analysis technique to efficiently test power-gating structures that provide intermediate power-off modes. In particular... View full abstract»

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  • Scan Attacks and Countermeasures in Presence of Scan Response Compactors

    Publication Year: 2011, Page(s):19 - 24
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (685 KB) | HTML iconHTML

    The conflict between security and testability is still a concern of hardware designers. While secure devices must protect confidential information from unauthorized users, quality testing of these devices requires the controllability and observability of a substantial quantity of embedded information, and thus may jeopardize the data confidentiality. Several attacks using the test infrastructures ... View full abstract»

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  • Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs

    Publication Year: 2011, Page(s):25 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (887 KB) | HTML iconHTML

    This paper proposes how the static linearity test method for DAC-ADC pairs using two low-quality signals can be optimized in terms of the used memory resources. The test is split into small segments so that the full histograms can be replaced by small ones. In the case of 16-bit ADC, the histogram memory requirement of an unoptimized algorithm is 131072 bytes while the proposed optimization cuts i... View full abstract»

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  • Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation

    Publication Year: 2011, Page(s):33 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1714 KB) | HTML iconHTML

    Dynamic testing of high-resolution Sigma Delta (ΔΣ) Analog-to-Digital converters (ADCs) is extremely challenging and expensive since it requires the use of spectrally pure stimulus with at least lOdB better signal-to-noise ratio (SNR) and total harmonic distortion (THD) than the ADC under test. This paper presents a low cost model parameter estimation based test and diagnosis methodo... View full abstract»

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  • A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager

    Publication Year: 2011, Page(s):39 - 44
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (443 KB) | HTML iconHTML

    This paper presents a low-cost pre- and post-bond self-testing and calibration methodology for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The basic idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of the internal digital-to-analog converter (DAC) capacitor array. During the... View full abstract»

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  • Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

    Publication Year: 2011, Page(s):45 - 50
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield, especially for larger stack sizes. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy. First, a analytical mode... View full abstract»

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  • DfT Architecture for 3D-SICs with Multiple Towers

    Publication Year: 2011, Page(s):51 - 56
    Cited by:  Papers (20)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (478 KB) | HTML iconHTML

    Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on... View full abstract»

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  • Power Aware Post-manufacture Tuning of Analog Nanocircuits

    Publication Year: 2011, Page(s):57 - 62
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB) | HTML iconHTML

    Process variations play a critical role in determining performance of scaled CMOS and other non-CMOS nanodevices. In this paper a power conscious post manufacture tuning technique is proposed for robust analog circuit fabrication with nanodevices in the presence of process variations. The response of the circuit to an optimized test signal is captured and using regression models, the proposed algo... View full abstract»

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  • Tomographic Testing and Validation of Probabilistic Circuits

    Publication Year: 2011, Page(s):63 - 68
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1130 KB) | HTML iconHTML

    Some emerging technologies for building computers depend on components and signals whose behavior, under normal or fault conditions, is probabilistic. Examples include stochastic and quantum computing circuits, and conventional nano electronic circuits subject to design, manufacturing or environmental errors. Problems common to these technologies are testing and validation, which require determini... View full abstract»

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  • Fault Masking and Diagnosis in Reversible Circuits

    Publication Year: 2011, Page(s):69 - 74
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (319 KB) | HTML iconHTML

    Reversible logic is a promising design methodology, particularly in the scope of quantum computing, for extremely low power consumption by elimination of power dissipation due to information loss. Anticipated high fault rates for future technologies raise demand for fault tolerance in reversible logic. In this paper we propose fault masking techniques (to prevent error propagation) for reversible ... View full abstract»

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  • Extraction of EVM from Transmitter System Parameters

    Publication Year: 2011, Page(s):75 - 80
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (778 KB) | HTML iconHTML

    Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. Since EVM is analytically related to system impairments, which are typically measured in a production test environment, it can be eliminated from the test list if the relations be... View full abstract»

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  • A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution

    Publication Year: 2011, Page(s):81 - 86
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    This paper describes a test bus suitable for conveying analog and digital signals to/from an unlimited number of circuit nodes with almost unlimited time or voltage resolution, in contrast to analog buses which are unlimited only in voltage resolution. A strategy is described that extends a silicon-proven approach for BIST of jitter and delays in PLLs, to BIST of 'random' analog functions. A varie... View full abstract»

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