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Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on

Date 6-9 June 2011

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Displaying Results 1 - 25 of 61
  • [Front cover]

    Page(s): c1
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  • [Copyright notice]

    Page(s): ii
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  • AHS 2011 - Table of contents

    Page(s): iii - vii
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  • Conference organizers

    Page(s): ix
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  • Program Committee

    Page(s): x
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  • Tunneling through the technology barrier: Thinking small to get the biggest change in space capability

    Page(s): xi
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  • Exascale computing - An impossible challenge?

    Page(s): xii
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  • Adapting remote systems: Getting it right the second time

    Page(s): xiii
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  • MAESTRO: Orchestrating predictive resource management in future multicore systems

    Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (813 KB) |  | HTML iconHTML  

    In this position paper, we make a case for a novel framework called MAESTRO which predictively manages system resources in shared-memory parallel computing platforms built with advanced multicore processors. In such platforms, effectively coordinating the use of asymmetric shared system resources under complex program execution scenarios becomes hard. Current resource management strategies are mostly reactive and have limited awareness of an application's resource usage and asymmetry in hardware resources. For better resource management, MAESTRO monitors the program execution environment (hardware/OS) and application behaviors, learns useful knowledge from collected information, annotates the results of the learning to relevant program and system control structures, and makes resource management decisions such as task mapping and cache partitioning in a predictive manner. View full abstract»

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  • Resource optimization and deadlock prevention while generating streaming architectures from ordinary programs

    Page(s): 9 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB) |  | HTML iconHTML  

    This paper presents a methodology for generating streaming architectures from ordinary programs. It automatically identifies streaming relationships and translates them into parallel computational kernels connected with customized stream buffers. New optimizations are introduced that reduce resource utilization by automatically generating lower bounds on stream buffer sizes. The approach also statically analyzes the design for deadlock and determines appropriate strategies to guarantee prevention. The experimental results show 19-325% improvement in performance and 15-62% reduction in area over non-streaming designs of several software-defined radio applications. This framework allows system-level designers to develop optimized reconfigurable streaming architectures for FPGAs at compile-time. View full abstract»

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  • Multicore soc for on-board payload signal processing

    Page(s): 17 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    This paper introduces a new generic platform for onboard payload signal processing. The system is built up around an NoC with a bridge to an AMBA system which supports easy integration with existing AMBA based platforms. With the use of a pthreads interface the platform allows for simple programming and easy extension. For prototyping purposes, an implementation has been made on an FPGA together with a range of I/O options to assess its capabilities. SpaceWire and other interfaces support the extension of the demonstrator platform across multiple boards and allow to connect it to onboard networks and systems. This paper shows that novel and established chip architectures can be integrated in a way that combines their benefits, and represents a promising candidate architecture for future on-board processing platforms. View full abstract»

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  • Unifying manycore and FPGA processing with the RUSH architecture

    Page(s): 22 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1083 KB) |  | HTML iconHTML  

    Because of the constraints of space computing, the set of available processing technologies is limited. Conventionally, designers have had to choose from programmable rad-hard processors and fixed ASIC solutions. FPGAs provide significantly better power-performance efficiency than general purpose processors, but are more costly to program and are less flexible. For terrestrial applications, manycore processors have been adopted for a class of applications where both performance and flexible programmability are important metrics. Maestro, the first rad-hard manycore processor, has the potential to enable new capabilities for space computation. However, for many applications, certain timing-critical tasks still require the performance efficiency of an FPGA co-processor. Moreover, integrating such heterogeneous systems is challenging because the individual processing substrates have differing internal programming models. As a result, data sharing and dynamic workload scheduling across heterogeneous architectures are often suboptimal and hindered by poor scalability. The Rad-hard Unified Scalable Heterogeneous (RUSH) architecture is a heterogeneous processing platform with both a manycore chip and an FPGA. RUSH provides a unified programming model across both chips to allow for rapid development of scalable and efficient implementations. This paper overviews RUSH's technical approach and presents an example application: a WiMAX radio transceiver. View full abstract»

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  • Maximizing the accuracy of sound based tracking via a low-cost network of reconfigurable embedded nodes

    Page(s): 29 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    This paper presents an approach for optimizing the accuracy of data models produced based on data sampled through a network of embedded sensors. The method considers three orthogonal facets defining model precision: minimizing the sampling error of the individual embedded nodes, sampling sufficient data from distributed areas to correctly represent the phenomenon of interest, and meeting the timing delays that guarantee the timeliness of data. The three objectives are achieved by dynamically reconfiguring the architecture of the embedded nodes, and dynamically selecting the data transfer paths to the decision making nodes. Sound based trajectory tracking is used as a case study for the proposed approach. View full abstract»

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  • Reconfigurable Analog VLSI circuits for robot path planning

    Page(s): 36 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1771 KB) |  | HTML iconHTML  

    This paper presents robot path planning using reconfigurable Analog-Very-Large-Scale-Integrated (AVLSI) circuits. Existing research has shown that custom AVLSI circuits known as application-specific-integrated-circuits (ASICs) can theoretically be used for robot path planning. There are two main drawbacks to using custom ASICs: (1) circuit designs are fixed to some extent (not changeable) and (2) long design cycle/fabrication time (order of months). Reconfigurable analog circuits called Field Programmable Analog Arrays (FPAAs) have been used to implement a variety of AVLSI circuits in a short time (order of minutes). This paper presents initial hardware results using reconfigurable AVLSI circuits developed at Georgia Tech to implement a robot path planning algorithm. A simple toy problem is presented as a proof of concept. View full abstract»

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  • Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory

    Page(s): 44 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1696 KB) |  | HTML iconHTML  

    Optically reconfigurable gate arrays (ORGAs) have been developed as a type of high-fault-tolerance multi-context field programmable gate array for space applications under radiation-rich environments. However, although many configuration contexts can be stored on an ORGA device and can be implemented on its gate array dynamically in an extremely short time, several laser sources are necessary to address the configuration contexts. Since such lasers are always expensive and because such devices are easily damaged by surge current, reducing the number of lasers is an important factor. Therefore, this paper presents a proposal of a new optically reconfigurable gate array with a polymer-dispersed liquid crystal holographic memory. Under the ORGA, all configuration contexts can be addressed by half the number of lasers as there are reconfiguration contexts. This paper presents demonstration results of the optically re-configurable gate array obtained using a polymer-dispersed liquid crystal holographic memory. View full abstract»

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  • Research on design method of scalable Configurable IP Core

    Page(s): 50 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (603 KB) |  | HTML iconHTML  

    Aiming at improving the flexibility and reducing the cost of SOC system design, the design of configurable IP core is prerequisite. In this paper, we mainly design a scalable configurable IP core and its configurable interface circuit. We call it FDP (FuDan Programmable) Configurable IP Core. This IP Core meets the requirement of configuration and scalability. Based on FDP Configurable IP Core, we successfully embed it into SOC to realize the application of Evolvable Hardware. Meanwhile, in order to reduce the reconfiguration time and enhance the performance of the whole system, we adopt several methods such as pre-reading configuration and compression of configuration bit stream, to implement the hardware reconfiguration and realize the function effectively. Experimental results initially validate the feasibility and large potential of the embedded scalable Configurable IP Core. View full abstract»

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  • UNITRONICS: A novel bio-inspired fault tolerant cellular system

    Page(s): 58 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1361 KB) |  | HTML iconHTML  

    We cannot yet match the high degree of reliability that biological systems possess when building electronic systems, no matter how intelligent they are. While proposals to date to solve this problem have demonstrated the feasibility of the bio-inspired approach, the resulting systems were often unduly complex. This paper presents a radically new approach to building fault tolerant systems. It proposes a novel model that uses the characteristics and behaviour of unicellular organisms, such as those of bacteria and bacterial communities, to construct highly reliable electronic systems with online fault repair properties. It demonstrates the feasibility of using bio-inspired cellular arrays with built-in self-diagnostic and self-repair capability to construct complex electronic systems. View full abstract»

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  • Application-aware optimization of redundant resources for the reconfigurable self-healing eDNA hardware architecture

    Page(s): 66 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1075 KB) |  | HTML iconHTML  

    In this paper we are interested in the mapping of embedded applications on a dynamically reconfigurable self-healing hardware architecture known as the eDNA (electronic DNA) architecture. The architecture consists of an array of cells interconnected through a 2D-mesh topology. Each cell consists of a processor and an Arithmetic Logic Unit (ALU). Applications are modeled as task graphs. We propose a Tabu Search-based approach for the mapping of an application to the reconfigurable architecture, such that the performance is maximized. When faults occur, the self-healing moves the affected functionality to spare-cells. We optimize the number and placement of spare-cells such that the performance overhead is minimized in the fault-free scenario and the application degrades gracefully in case of faults. This has been done using three different spare-cell placement strategies. We use Monte Carlo simulation to determine the average performance overhead increase due to fault occurrences. The approach has been evaluated using a large number of benchmarks and have shown that the performance loss is reduced with 16% for the best spare-cell placement strategy. View full abstract»

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  • Radiation hardening by design: A novel gate level approach

    Page(s): 74 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    Soft errors induced by radiation, causing malfunctions in electronic systems and circuits, have become one of the most challenging issues that impact the reliability of the modern processors even in sea-level applications. In this paper we present two novel radiation-hardening techniques at Gate-level. We present a Single-Event-Upset (SEU) tolerant Flip-Flop design with 38% less power overhead and 25% less area overhead at 65nm technology comparing to the conventional Triple Modular Redundancy (TMR) for Flip-Flop design. We also present an SEU-tolerant Clock-Gating scheme with less than 50% area-power overheads and no performance penalty comparing to the conventional TMR for clock-gating. Our simulations show that the proposed schemes can recover from SEU errors in 99% of the cases. View full abstract»

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  • Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors

    Page(s): 80 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (729 KB) |  | HTML iconHTML  

    This paper describes an approach that allows using the potential of reconfigurable processors in an efficient and adaptive manner. Some architectural design decisions (e.g., the provided memory interface, number of ports, and bit-width per port) have a strong impact on the efficiency, whereas other design decisions (e.g., how the reconfigurable fabric is used to implement application-specific accelerators) have an impact on the adaptivity that the reconfigurable processor can provide. Therefore, we will present and discuss different design decision alternatives for reconfigurable processor architectures. After introducing the basic concepts and principal advantages of reconfigurable processors, the promising concept of modular Special Instructions (SIs) is presented as a general approach to achieve a high adaptivity in reconfigurable processors. This paper shows how these modular SIs can be used to achieve high adaptivity and which scenarios benefit from such adaptive processing behavior. Afterwards, the basic requirements and infrastructure to operate modular SIs in an efficient and adaptive manner are presented in detail and analyzed. To exploit the adaptivity that is provided by modular SIs, a run-time system is required to decide how the reconfigurable processor shall react on changing requirements and situations. This paper gives a general overview of the steps that need to be performed by such a run-time system. Finally, the adaptive reconfigurable RISPP processor that is based on the presented architectural design decisions, the concept of modular special instructions, and the controlling run-time system is evaluated. View full abstract»

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  • Run-time resource instantiation for fault tolerance in FPGAs

    Page(s): 88 - 95
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (730 KB) |  | HTML iconHTML  

    The scaling of IC feature sizes has increased the integration capability and allowed the design of large systems in one single chip. This improvement has also contributed to reconfigurable circuits densities, such as the Xilinx Virtex-4 FPGA, which exceeds ten million gates. In spite of that, circuit miniaturization will also increase defect and fault rates in such high magnitude that a fault tolerance approach will be mandatory for the proper functioning of any circuit in future technologies. To cope with manufacturing defects and permanent faults in FPGAs, this paper presents an approach that dynamically instantiates the resources in non-faulty regions of the FPGA. The run-time control system works around the faulty FPGA region and instantiates the logic and routing units in non-faulty ones. This allows one to sustain performance by preserving the amount of resources. Moreover, the proposed fault tolerance approach is transparent to the user. For each configuration the control system automatically instantiates the units according to the application's data flow graph and the defect and fault map. View full abstract»

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  • A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion

    Page(s): 96 - 103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1164 KB) |  | HTML iconHTML  

    Hardware virtualization is a well known technique in processor based hardware architectures for abstraction of the complexity of an underlying hardware from the programmer. Not only processor based hardware, especially Field Programmable Gate Arrays (FPGA), comes with a high complexity and the exploitation for developers suffer from this fact. Each change in the hardware e.g. through an introduction of a new series results in a re-design of the applications. Therefore, a novel concept for FPGA hardware virtualization is introduced in this paper. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent from the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform, describes the tool chain for the virtual FPGA and introduces with Core Fusion a novel technique that improves the utilization of the virtual FPGA. View full abstract»

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  • Enabling FPGAs for future deep space exploration missions: Improving fault-tolerance and computation density with R3TOS

    Page(s): 104 - 112
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    Future deep space exploration missions will require small, lightweight, low-power, fault-tolerant, autonomous and durable onboard electronic systems. In this paper we present R3TOS, a novel approach for online scheduling and allocating different pieces of circuitry onto partially reconfigurable FPGAs to match the specific computation needs at all times. R3TOS targets two main objectives: (i) obtain the best performance per unit of device's area and per unit of consumed energy and, (ii) minimize the impact of device's degradation on performance. View full abstract»

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  • The future of embedded systems at ESA: Towards adaptability and reconfigurability

    Page(s): 113 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB) |  | HTML iconHTML  

    Embedded devices used in the space industry have to face stringent requirements imposed by their deployment environment, namely high reliability, limited resources, and challenges in heat dissipation. In addition, to make matters worse, the demand for advanced processing capability is growing steadily to meet future exploration and deep space mission requirements. At the European Space Agency, ongoing studies are focusing the use of reconfigurable and adaptable systems to help finding solutions to the aforementioned issues as well as to how reconfigurable systems can aid in mission cost reductions. After giving a general overview of the efforts spent in this direction, this paper presents two concrete examples of on going research activities funded by the European Space Agency. View full abstract»

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