Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

18-23 Oct. 1998

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  • Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

    Publication Year: 1998
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    Freely Available from IEEE
  • Microelectromechanical systems (MEMS) tutorial

    Publication Year: 1998, Page(s):432 - 441
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (971 KB)

    Using the fabrication techniques and materials of microelectronics as a basis, MEMS processes construct both mechanical and electrical components. Mechanical components in MEMS, like transistors in microelectronics, have dimensions that are measured in microns and numbers measured from a few to millions. MEMS is not about any one single application or device, nor is it defined by a single fabricat... View full abstract»

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  • Scaling deeper to submicron: on-line testing to the rescue

    Publication Year: 1998, Page(s): 1139
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (71 KB)

    First Page of the Article
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  • Author index

    Publication Year: 1998, Page(s):1178 - 1179
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    Freely Available from IEEE
  • An introduction to area array probing

    Publication Year: 1998, Page(s):277 - 281
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    The semiconductor industry's move to area array I/O wafers is accelerating, demanding that wafer probe professionals become knowledgeable with the considerations and techniques for probing these wafers. Area array probing has been practised within ISM for over two decades. From that experience, this overview will provide an awareness of the factors, techniques and methods associated with array are... View full abstract»

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  • Fine pitch (45 micron) P4 probing

    Publication Year: 1998, Page(s):272 - 276
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    We describe the P4 (photolithographic pattern plating process) probe card. This technology has enabled very fine (45 micron) pitch, high pin count (more than 1000 pins) and high speed (>2 GHz) probing. We summarize the design, the manufacturing process, standard specifications and performance properties of the P4 probe card. The results of contact tests are also described View full abstract»

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  • Cost of test reduction

    Publication Year: 1998, Page(s):265 - 270
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    IC manufacturers are engaged in a continuous process of complexity increase (Moore's law) and at the same time of price decrease-not to forget the search for quality. The cost aspect is particularly important for microcontroller (MCU) manufacturers, since these devices are produced in volume, and are used in cost-sensitive equipment (automotive, appliances, toys, etc.). This is why STMicroelectron... View full abstract»

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  • Probabilistic mixed-model fault diagnosis

    Publication Year: 1998, Page(s):1084 - 1093
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB)

    Previously-proposed strategies for VLSI fault diagnosis have suffered from a variety of self-imposed limitations. Some techniques are limited to a specific fault model, and many will fail in the face of any unmodeled behavior or unexpected data. Others apply ad-hoc or arbitrary scoring mechanisms to fault candidates, making the results difficult to interpret or to compare with the results from oth... View full abstract»

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  • Temperature control of a handler test interface

    Publication Year: 1998, Page(s):114 - 118
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A very compact electrical test contactor assembly design for a handler is described that gives a means to better match the temperature of the contactors (-60 degC to 160 degC) and the devices under test (DUTs). The resulting design aims for tight temperature control (±1 degC) of DUTs while minimizing the electrical transmission path length (~2.5 cm). A high thermal conductivity plate uses d... View full abstract»

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  • Multi-output one-digitizer measurement

    Publication Year: 1998, Page(s):258 - 264
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    Reducing test costs is a constant issue for semiconductor manufacturers. One key to reducing test cost is reducing test time. Parallel testing is widely employed for this purpose, but the cost of the parallel test system itself is generally high, and simpler test systems would bring further substantial reductions in test cost. We have developed test system structures in which the number of digitiz... View full abstract»

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  • Maximizing handler thermal throughput with a rib-roughened test tray

    Publication Year: 1998, Page(s):109 - 113
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A new design feature of an integrated circuit (IC) test handler tray is described that significantly improves the convective heat transfer to the tray and the IC devices in the tray. The improved tray incorporates vertically protruding ribs which breakup thermal boundary layers and enhance mixing. High-speed, tray-based handlers can consequently warm or cool trays of devices at substantially faste... View full abstract»

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  • Reduction of errors due to source and meter in the nonlinearity test

    Publication Year: 1998, Page(s):254 - 257
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    Nonlinearity test is required for many products of various applications, such as in consumer and is difficult to rest when sources and meters are nonlinear. A novel method using digital signal processing (DSP) techniques is presented to reduce the errors introduced by nonlinear source and meter. It uses the Taylor series representation to model the nonlinearity of source, meter, and device under l... View full abstract»

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  • A diagnostic test generation procedure for synchronous sequential circuits based on test elimination

    Publication Year: 1998, Page(s):1074 - 1083
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    We propose a procedure for generating test sequences for diagnosis of synchronous sequential circuits based on stuck-at faults. The test generation procedure avoids the conventional fault-oriented test generation by observing that a sequence to distinguish two faults can be obtained from a sequence that detects both of the faults (such as a test sequence for fault detection) by changing the sequen... View full abstract»

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  • Defect level prediction for IDDQ testing

    Publication Year: 1998, Page(s):900 - 909
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    A problem with IDDQ testing is its inability to predict defect level. This paper classifies defects detected by IDDQ testing into two categories: those that can be modeled by stuck-at-fault (SAF) model and those that can not be modeled by SAF, based on statistical analysis of production failures and field failures. A new approach for curve fitting to a classical model is pres... View full abstract»

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  • Designing for scan test of high performance embedded memories

    Publication Year: 1998, Page(s):101 - 108
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    The addressing and clocking schemes in PowerPCTM microprocessor embedded memories present modeling challenges. The ability of most scan based test tools to accurately generate test patterns for these embedded memories is limited. What is needed is aggressive Design for Test implementations that can help the test generation tools. In this paper we present our experiences in the design, m... View full abstract»

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  • When “almost” is good enough: a fresh look at DSP clock rates

    Publication Year: 1998, Page(s):249 - 253
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    Traditional DSP mixed-signal coherent test techniques require precise frequency ratios. This paper explores the limits of this requirement to define how closely rates must match ideal ratios to obtain proper results. Both worst-case and typical situations are considered. Worst-case conditions allow errors on the order of one part in 200,000,000,000. While small, this error tolerance allows changes... View full abstract»

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  • Compact two-pattern test set generation for combinational and full scan circuits

    Publication Year: 1998, Page(s):944 - 953
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. The test s... View full abstract»

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  • An almost full-scan BIST solution-higher fault coverage and shorter test application time

    Publication Year: 1998, Page(s):1065 - 1073
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper illustrates that for existing scan-based Built-In Self-Test (BIST) architectures under the pseudo-random testing scheme, scanning all flip-flops may not be the best strategy for achieving high fault coverage with a practical limit on test length. In general, for scan-based BIST, not scanning flip-flops with relatively high pseudo-random observabilities through the primary outputs may in... View full abstract»

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  • Quad DCVS dynamic logic fault modeling and testing

    Publication Year: 1998, Page(s):356 - 362
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Dynamic logic fails differently than static logic. Fault modeling with Quad Differential Cascode Voltage Switch (DCVS) is studied in simulation and hardware. Appropriate test methods are examined yielding results relevant to general dynamic logic, DCVS, and pass gate DCVS View full abstract»

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  • Current signatures: application [to CMOS]

    Publication Year: 1998, Page(s):1168 - 1177
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Applica... View full abstract»

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  • Learning to knit SOCs profitably

    Publication Year: 1998
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    General solutions for SOC (System-on-Chip) test appear to demand new models of partnership among core designers, system integrators, test system manufacturers, test engineers. and process engineers. Each of these partners possesses unique value to contribute to the fundamental understanding that will enable the successful management of the interactions among disparate circuits. Progress towards th... View full abstract»

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  • ATPG in practical and non-traditional applications

    Publication Year: 1998, Page(s):632 - 640
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    There exist many different problems in the design automation realm that have no simple solution. Often a problem requires some kind of search through a potential solution space to see if one or more examples exist to prove or disprove a supposition. In many of these cases it is possible to use an ATPG engine to perform an examination of the search space. This paper describes many of the various ap... View full abstract»

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  • Novel optical probing technique for flip chip packaged microprocessors

    Publication Year: 1998, Page(s):740 - 747
    Cited by:  Papers (30)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    A novel infrared (IR) optical probing technique which provides fast and direct access to diffusion (p-n junction) nodes directly through the silicon substrate is described. The optical probing technology allows waveform measurements to be obtained directly from internal nodes of a CMOS integrated circuit (IC). These measurements can be made on C4 (Flip Chip) mounted ICs in stand-alone, MCM or any ... View full abstract»

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  • Detecting resistive shorts for CMOS domino circuits

    Publication Year: 1998, Page(s):890 - 899
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1004 KB)

    We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best for small CMOS domino gates. Keep... View full abstract»

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  • BIST: required for embedded DRAM

    Publication Year: 1998
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    In the virtual component (VC) integration business, the embedded DRAM is a key VC to realize high bit density and high bandwidth performance, thus the low-cost testing of DRAM-integrated LSI is an emerging problem. The DRAM test usually includes a fail-bit (address) search to repair the memory cell defects with redundancy, requiring long time for wafer probing. A DRAM BIST drastically reduces time... View full abstract»

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