2011 Electronic System Level Synthesis Conference (ESLsyn)

5-6 June 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Title page]

    Publication Year: 2011, Page(s): 1
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  • [Copyright notice]

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  • Table of contents

    Publication Year: 2011, Page(s):1 - 2
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  • Welcome to ESLsyn 2011

    Publication Year: 2011, Page(s):1 - 4
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  • Session 1: Co-design — Part I

    Publication Year: 2011, Page(s): 1
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  • A hardware/software codesign template library for design space exploration

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB) | HTML iconHTML

    The ability to map a high level algorithm either to hardware or software simplifies design space exploration of cyber-physical systems. Thereby, low level tools can be utilized for accurate design parameter estimation, which helps to evaluate the effect of system level design decisions. Especially complex data structures pose a problem in this context. The different structure of memory in hardware... View full abstract»

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  • Unifying process networks for design of cyber physical systems

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB) | HTML iconHTML

    Design of cyber-physical systems poses new challenges. Design at the level of a whole cyber-physical system includes design issues such as formal and abstract specification, design space exploration, optimization, and verification. A particular challenge is the formal and abstract representation of whole cyber-physical systems including both physical and cyber components. The objective of this pap... View full abstract»

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  • Session 2: FPGAs and synthesis — Part I

    Publication Year: 2011, Page(s): 1
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  • Just-in-time compilation for FPGA processor cores

    Publication Year: 2011, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    Portability benefits have encouraged the trend of distributing applications using processor-independent instructions, a.k.a. bytecode, and executing that bytecode on an emulator running on a target processor. Transparent just-in-time (JIT) compilation of bytecode to native instructions is often used to increase application execution speed without sacrificing portability. Recent work has proposed d... View full abstract»

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  • FPGA-specific optimizations by partial function evaluation

    Publication Year: 2011, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (478 KB) | HTML iconHTML

    Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspe... View full abstract»

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  • Session 3: Modelling

    Publication Year: 2011, Page(s): 1
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  • System synthesis from AADL using Polychrony

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (853 KB) | HTML iconHTML

    The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in th... View full abstract»

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  • SCIPX: A systemc to IP-Xact extraction tool

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (357 KB) | HTML iconHTML

    The IP-Xact formalism (IEEE 1685 standard), was introduced to help assemble IP components from distinct sources into an integrated design. Components would be expressed in high-level HDLs such as SystemC, and so should be the full design after composition. Currently, while components exist at SystemC level, they generally do not provide any local IP-Xact structural interface representation. The pr... View full abstract»

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  • From design-time concurrency to effective implementation parallelism: The multi-clock reactive case

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (181 KB) | HTML iconHTML

    We have defined a full design flow starting from high-level domain specific languages (Simulink, SCADE, AADL, SysML, MARTE, SystemC) and going all the way to the generation of deterministic concurrent (multi-threaded) executable code for (distributed) simulation or implementation. Based on the theory of weakly endochronous systems, our flow allows the automatic detection of potential parallelism i... View full abstract»

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  • Session 4: Co-design — Part II

    Publication Year: 2011, Page(s): 1
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  • A framework for generic HW/SW communication using remote method invocation

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB) | HTML iconHTML

    Implementation of communication between different tasks of a concurrent embedded system is a challenging problem. The aim of our work is to support the refinement and relocation of tasks onto different execution units, such as processors running different operating system or even dedicated hardware. For this purpose communication should be transparent and as independent as possible from the underl... View full abstract»

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  • Kahn process networks applied to distributed heterogeneous HW/SW cosimulation

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (366 KB) | HTML iconHTML

    Heterogeneous, distributed hardware/software cosimulation techniques using the backplane method encounter complex interface protocols for simulator communication and synchronization, limiting their adoption or abstraction. We simplify the dynamics of backplane cosimulation to the properties of a Kahn Process Network (KPN), such that tokens of the KPN are interpolated events. This simplifies the ba... View full abstract»

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  • Session 5: FPGAs and synthesis — Part II

    Publication Year: 2011, Page(s): 1
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  • Enabling the synthesis of very long operation properties

    Publication Year: 2011, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    In previous work, the high-level synthesis of operation properties has been proposed. In this work, we improve the existing algorithms in order to allow the synthesis of more efficient hardware models. Especially for very long properties no model could be generated before, because both the runtime of the synthesis process and the amount of used hardware resources were prohibitively high. The propo... View full abstract»

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  • Increasing computational density of application-specific systems

    Publication Year: 2011, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (122 KB) | HTML iconHTML

    Application-specific systems are increasingly being deployed on reconfigurable computing platforms such as the field-programmable gate array (FPGA). These systems can integrate many disparate computing elements, and often contain soft processors hosting application components. Soft processors are sequential, synchronous devices with low computational density, and are not capable of exploiting the ... View full abstract»

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  • Session 6: System design

    Publication Year: 2011, Page(s): 1
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  • Application-specific codesign platform generation for digital mockups in cyber-physical systems

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (713 KB) | HTML iconHTML

    The testing of cyber-physical systems requires validating device functionality for a wide range of operating conditions. The environment with which the cyber-physical device interacts, such as lungs for a medical ventilator device or a busy freeway for an autonomous vehicle, may be complex and subsequently difficult to explore all possible configurations. Computer simulations that utilize device a... View full abstract»

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  • A unifying interface abstraction for accelerated computing in sensor nodes

    Publication Year: 2011, Page(s):1 - 6
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (283 KB) | HTML iconHTML

    Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low-power FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/so... View full abstract»

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