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Industrial Embedded Systems (SIES), 2011 6th IEEE International Symposium on

Date 15-17 June 2011

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Displaying Results 1 - 25 of 51
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • [Copyright notice]

    Page(s): iii
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  • Table of contents

    Page(s): v - ix
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  • Message from the conference chairs

    Page(s): xi
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  • Committees

    Page(s): xiii - xvi
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  • HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs

    Page(s): 1 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3519 KB) |  | HTML iconHTML  

    Nowadays industrial monoprocessor and multiprocessor systems make use of hardware floating-point units (FPUs) to provide software acceleration and better precision due to the necessity to compute complex software applications. This paper presents the design of an IEEE-754 compliant FPU, targeted to be used with ARM Cortex-M1 processor on FPGA SoCs. We face the design of an AMBA-based decoupled FPU in order to avoid changing of the Cortex-M1 ARMv6-M architecture and the ARM compiler, but as well to eventually share it among different processors in our Cortex-M1 MPSoC design. Our HW-SW implementation can be easily integrated to enable hardware-assisted floating-point operations transparently from the software application. This work reports synthesis results of our Cortex-M1 SoC architecture, as well as our FPU in Altera and Xilinx FPGAs, which exhibit competitive numbers compared to the equivalent Xilinx FPU IP core. Additionally, single and double precision tests have been performed under different scenarios showing best case speedups between 8.8× and 53.2× depending on the FP operation when are compared to FP software emulation libraries. View full abstract»

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  • Multi-criteria optimization for mapping programs to multi-processors

    Page(s): 9 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (995 KB) |  | HTML iconHTML  

    Finding tradeoffs in design space is naturally formulated as a multicriteria optimization problem. In this paper, we model tradeoffs between communication cost and the balance of processor workloads for the problem of mapping applications to processors in a multicore environment. We formulate several query strategies for finding Pareto optimal and approximately Pareto optimal solutions to the mapping problem using a constraint solver as a time-bounded oracle. Each of the strategies directs the oracle through the search space in a different manner. We evaluate the efficiency of these strategies on a series of synthetic benchmarks, and on two industrial applications, a video noise reduction, and an image demosaic color filtering. The results indicate a significant tradeoff between precision and computation time, and a corresponding benefit to time-bounded queries. View full abstract»

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  • Contract-based dynamic task management for mixed-criticality systems

    Page(s): 18 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (978 KB) |  | HTML iconHTML  

    The use of models is becoming increasingly prominent in the development processes for safety and time critical systems (e.g. in automotive or aerospace). However, oftentimes the models of a component, its implementation properties and execution parameters are only loosely coupled. This missing association complicates system maintainability and becomes an issue with increasing system flexibility. This paper presents a runtime environment closely coupling design-time component models with the execution parameters of the specific component also enabling runtime monitoring of implementation properties. Together with a previously published admission control scheme, this enables tight coupling of component-wise design-time modelling, system analysis and runtime configuration, enabling software flexibility also in mixed-criticality systems. View full abstract»

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  • Robustness in real-time systems

    Page(s): 28 - 34
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    We review several aspects of robustness of real-time systems, and present recent results on the robust verification of timed automata. View full abstract»

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  • Towards preemption control using CPU frequency scaling in sporadic task systems

    Page(s): 35 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (949 KB) |  | HTML iconHTML  

    Preemptions in real-time systems scheduling typically lead to variations in task execution times, increase the temporal overhead required for various RTOS related operations and may even cause unschedulability. We examine the preemption behavior of sporadic tasks scheduled under the Fixed Priority Scheduling (FPS) policy, and evaluate the possibility of using CPU frequency scaling for preemption control. We propose an online heuristic-based algorithm, of linear complexity, to control the number of preemptions in a sporadic task system using CPU frequency scaling. Evaluation results show that CPU frequency scaling is an attractive option to control the preemption behavior of real-time sporadic task systems. View full abstract»

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  • Towards adaptive hierarchical scheduling of overloaded real-time systems

    Page(s): 39 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    In a hierarchical scheduling framework, a resource can be shared among modules with different criticality levels. In our recently introduced adaptive hierarchical scheduling framework, modules receive a dynamic portion of the CPU during run-time. While providing temporal isolation is one of the main advantages of hierarchical scheduling, in an adaptive framework, for example when the CPU is overloaded, the higher priority modules can violate timing guarantees of the lower priority modules. However, the priorities of modules are assigned based on parameters other than the module criticality levels. For example the priority is often assigned according to periods and deadlines of tasks to increase the CPU utilization assuming static systems, i.e. modules parameters do not change during runtime. In an overload situation the high criticality modules should be superior to the low criticality modules in receiving resources. In this paper, extending our adaptive framework, we propose two techniques for controlling the CPU distribution among modules in an overload situation. We are taking another step towards having a complete adaptive hierarchical scheduling framework by incorporating an overload controller into our framework. View full abstract»

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  • A statistical response-time analysis of complex real-time embedded systems by using timing traces

    Page(s): 43 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (746 KB) |  | HTML iconHTML  

    Real-time embedded systems are becoming ever more complex, and we are reaching the stage where even if static Response-Time Analysis (RTA) was feasible from a cost and technical perspective, the results are overly pessimistic making them less useful to the practitioner. When combined with the fact that most timing analysis tends to be statistical in nature, this suggests there should be a move toward statistical RTA. However, to make such analysis useful, it is imperative that we have evidence that the statistical RTA and the information analyzed is sufficiently accurate. In this paper we present and validate a technique for statistical RTA that can cope with systems that are complex from both a size and tasks' dependencies perspective. This claim is backed up by our evaluation using information from real industrial control systems. View full abstract»

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  • An IDE for component-based design of embedded real-time software

    Page(s): 47 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1087 KB) |  | HTML iconHTML  

    This paper describes work in progress on a tool for component-based design of embedded real-time software. The tool supports graphical modeling of software systems using concurrent reactive objects and components, as well as generation of C code from the model. The resulting application code can then be combined with a lightweight kernel for execution on bare metal. View full abstract»

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  • Improving model-based verification of embedded systems by analyzing component dependences

    Page(s): 51 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (777 KB) |  | HTML iconHTML  

    Embedded systems in automobiles become increasingly complex as they are intended to make vehicles even more safe, comfortable, and efficient. International norms like ISO 26262 and IEC 61165 postulate methods for the development and verification of safety critical systems. These standards should ensure that the dependability and quality of the embedded systems is maintained while their complexity and interdependence increases. Yet, the standards do not contain concrete methods or tools for their fulfillment. As concerns classic techniques for dependability analysis they either base on system analysis by means of Markov analysis or on reliability estimation from a usage perspective. Treating the system only from one perspective, however, is a drawback as the system analysis neglects functional or non-functional dependences of the system. These dependences can directly influence the reliability in the field usage. In this paper we present our approach to combine component dependency models with usage models to overcome these deficiencies. It is possible to identify usage scenarios which aim for critical dependences and to analyze the interaction of components inside the system. On the other hand usage scenarios can be assessed whether they meet the desired verification purpose. The component dependency models reveal dependences that were not identified before, because it allows the extraction of implications across functional and non functional dependences like memory, timing and processor utilization. View full abstract»

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  • Towards runtime testing in automotive embedded systems

    Page(s): 55 - 58
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    Runtime testing is a common way to detect faults during normal system operation. To achieve a specific diagnostic coverage runtime testing is also used in safety critical, automotive embedded systems. In this paper we propose a test architecture to consolidate the hardware resource consumption and timing needs of runtime tests and of application and system tasks in a hard real-time embedded system as applied to the automotive domain. Special emphasis is put to timing requirements of embedded systems with respect to hard real-time and concurrent hardware resource accesses of runtime tests and tasks running on the target system. View full abstract»

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  • Synthesis of diagnostic techniques based on an IEC 61508-aware metamodel

    Page(s): 59 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (990 KB) |  | HTML iconHTML  

    Safety standards, such as IEC 61508, play an important role in assuring the safety of embedded systems. Since model-driven development (MDD) is also gaining importance in the development process of these systems, an integration of the standards with existing modeling theory is promising. However, one of the basic building blocks of MDD, the metamodels, have not been made “standard-aware” yet. This paper presents a first step of such an integration by using a standard-aware meta-model to synthesize diagnostic techniques. This is an important task, because the correct selection and implementation of these techniques is traditionally a manual, labor-intensive task. The necessary steps of such an integration are discussed, including the definition of the metamodel, the formulation of an algorithm to select the right diagnostic techniques, and the implementation of code generation. View full abstract»

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  • Generation of correct-by-construction code from design models for embedded systems

    Page(s): 63 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (797 KB) |  | HTML iconHTML  

    In a model-driven engineering development process that focuses on guaranteeing that extra-functional concerns modeled at design level are preserved at platform execution level, the task of automated code generation must produce artifacts that enable back-annotation activities. In fact when the target platform code has been generated, quality attributes of the system are evaluated by appropriate code execution monitoring/analysis tools and their results back-annotated to the source models to be extensively evaluated. Only at this point the preservation of analysed extra-functional aspects can be either asserted or achieved by re-applying the code generation chain to the source models properly optimized according to the evaluation results. In this work we provide a solution for the problem of automatically generating target platform code from source models focusing on producing code artifacts that facilitate analysis and enable back-annotation activities. Arisen challenges and solutions are described together with completed and planned implementation of the proposed approach. View full abstract»

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  • State Design Pattern Implementation of a DSP processor: A case study of TMS5416C

    Page(s): 67 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (821 KB) |  | HTML iconHTML  

    This paper presents an empirical study of the impact of State Design Pattern Implementation on the memory and execution time of popular fixed-point DSP processor from Texas Instruments; TMS320VC5416. Actually, the object-oriented approach is known to introduce a significant performance penalty compared to classical procedural programming. One can find the studies of the object-oriented penalty on the system performance, in terms of execution time and memory overheads in the literature. Since, to the author's best knowledge the study of the overheads of Design Patterns (DP) in the embedded system programming is not widely published in the literature. The main contribution of the paper is to bring further evidence that embedded system software developers have to consider the memory and the execution time overheads of DPs in their implementations. The results of the experiment show that implementation in C++ with DP increases the memory usage and the execution time but meanwhile these overheads would not prevent embedded system software developers to use DPs. View full abstract»

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  • Architecture of an embedded time gateway between PTP and SNTP

    Page(s): 71 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1708 KB) |  | HTML iconHTML  

    This paper deals with time synchronization in mixed network infrastructures for automation of industrial and electric plants, where old devices, which retrieve time information with the well-known NTP, must coexist with new IEEE1588 PTP compliant devices. Since PTP and NTP use very different time representations and synchronization strategies, an easy integration is quite difficult and requires additional hardware. The paper describes a transparent Time Gateway that is able to interface SNTP devices with a PTP synchronization domain (PTP devices and PTP switches). The Time Gateway has been realized with an embedded system based on an FPGA with a soft processor and an open source operating system. Preliminary experimental results show the feasibility of the proposed architecture, even if some improvements may be needed to match the time synchronization accuracy required by the legacy SNTP devices. View full abstract»

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  • Model-based design of embedded control software for hybrid vehicles

    Page(s): 75 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1185 KB) |  | HTML iconHTML  

    In the last decades, model based methodologies have become the mainstay of research on embedded systems development. The availability of mature computer aided tools and of well-settled industrial practices has promoted the adoption of these methodologies in large companies, which are able to amortize the cost on a large volume of products. On the contrary, the cost of software licenses and of staff training often discourages their application in small and medium enterprises. In this paper, we present a model based methodology entirely based on the adoption of open source software tools. We have applied this methodology to a real case study provided by our industrial partner proving its effectiveness. View full abstract»

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  • Portability analysis of an M-JPEG decoder IP from OpenCores

    Page(s): 79 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (865 KB) |  | HTML iconHTML  

    The reuse of predefined Intellectual Property (IP) can shorten development times and help the designer to meet time-to-market requirements for embedded systems. Using FPGA IP in a proper way can also mitigate the component obsolescence problem. System migration between devices is unavoidable, especially for long lifetime embedded systems, so IP portability becomes an important issue for system maintenance. This paper presents a case study analyzing the portability of an FPGA-based M-JPEG decoder IP. The lack of any clear separation between computation and communication is shown to limit the decoder's portability with respect to different communication interfaces. Technology and tool dependent firmware IP components are often supplied by FPGA vendors. It is possible for these firm IP components to reduce development time. However, the use of these technology and tool dependent firmware specifications within the M-JPEG decoder is shown to limit the decoder's portability with respect to development tools and FPGA vendors. View full abstract»

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  • Thread-level speculation as an optimization technique in Web Applications — Initial results

    Page(s): 83 - 86
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    Web Applications have become increasingly popular as they allow developers to use an uniform platform for user interactions. The dynamic programming language JavaScript used in most Web Applications has performance penalties, that have been addressed by traditional optimization techniques. We have found that while the performance gain of such techniques are positive for a set of established benchmarks, it often fails to improve the performance of real-life Web Applications. We suggest Thread-Level Speculation (TLS) at the JavaScript function level to automatically extract parallelism to gain performance. There have been multiple TLS proposals in both hardware and software, but little work has been done within JavaScript. Currently we are implementing our TLS ideas in a state-of-the-art JavaScript engine targeted for embedded mobile devices. View full abstract»

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  • A methodology for designing energy-aware secure embedded systems

    Page(s): 87 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (401 KB) |  | HTML iconHTML  

    Bringing security aspects in earlier phases of development is one of the major shifts in software development trend. Model-driven development which helps with raising the abstraction level and facilitating earlier analysis and verification is a promising approach in this regard and there have been several efforts on modeling security aspects. However, the issue is that when it comes to embedded systems, non-functional requirements such as security are so interconnected that in order to satisfy one, trade-off analysis with other ones are necessary. Energy consumption is one of these requirements which is of great importance in embedded systems domain due to resource limitations that these systems have. In this paper, focusing on security and energy consumptions we propose a new methodology for model-driven design of embedded systems to bring energy measurements and estimations earlier in development phases and thus identify security design decisions that cause violations of specified energy requirements. View full abstract»

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  • Large drilling machine control code — Parallelisation and WCET speedup

    Page(s): 91 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3514 KB) |  | HTML iconHTML  

    Hard real-time applications in safety-critical domains - namely avionics, automotive, and machinery - require high-performance and timing analysability. We present research results of the parallelisation and WCET analysis of an industrial hard real-time application, i.e. the control code of a large drilling machine from BAUER Maschinen GmbH. We reached a quad-core speedup of 2.62 for the maximum observed execution time (MOET) and 1.93 on the WCET compared to the sequential version. For the WCET analysis we used the measurement-based WCET analysis tool RapiTime. View full abstract»

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  • A low cost, low power, high scalability and dependability processor-cluster platform

    Page(s): 95 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1167 KB) |  | HTML iconHTML  

    Nowadays, more and more applications are computing-intensive, such as search engines, online game servers, or even fMRI, used in medical examination. Supercomputers are setup to meet the computing demand as well as huge data storage. However, some applications favor computing power much more than data storage. To emphasize on providing computing power with low cost, low power, high scalability and dependability, this work presents a platform which involves a group of computing clusters. A cluster consists of up to 12 processors. A computing job is distributed to a group of processors for speed-up. Moreover, an FPGA may join for further acceleration. A set of front-end servers is responsible for job dispatching and maintains reliability. The system details are described. Current status and ongoing work are also reported. View full abstract»

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