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Faible Tension Faible Consommation (FTFC), 2011

Date May 30 2011-June 1 2011

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Displaying Results 1 - 25 of 35
  • [Copyright notice]

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    Freely Available from IEEE
  • Committees

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    Freely Available from IEEE
  • Program

    Page(s): iii - vi
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    Freely Available from IEEE
  • Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (734 KB) |  | HTML iconHTML  

    In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n- and p-MOS transistors, automatically biasing the stand-by gate-to-source voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks: a 2-terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors. View full abstract»

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  • Sizing low-voltage, low-power CMOS analog circuits

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (487 KB) |  | HTML iconHTML  

    The gm/ID methodology allows designing Low-Voltage Low-Power CMOS circuits without the need to iterate SPICE simulations. The methodology leads directly to optimal implementations provided clear objective can be laid down first. Generally the method proceeds according to the steps below: a) set-up look-up tables making use of Spice or BSIM (gm/ID's from 10 to 15 V-1 are considered primarily to minimize power). b) choose primary variables c) estimate gate lengths in accordance with desired gain and transit frequencies. d) evaluate parasitic capacitances. e) evaluate currents and widths taking advantage of specifications. Since closed-form solutions cannot be found generally in complex circuits, some assumptions may be required wherever necessary. f) re-iterate drain and width evaluations to get rid of the assumptions. g) check the result by running a circuit simulator like Spice. View full abstract»

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  • Nanoampere supply independent low-voltage current reference

    Page(s): 9 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (171 KB) |  | HTML iconHTML  

    Mixed signal integrated circuits require a form of current reference to properly bias the analog block. The use of advanced process technologies forces those circuits to operate at low voltage, and portable electronics demand operation at very low currents. Good power supply rejection is of paramount importance to reduce coupling of noise generated in the associated digital circuitry into the analog part. It is important then to count with current reference circuits that can operate with predictable performance in these conditions. View full abstract»

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  • A Vt independent voltage reference based on composite transistors operating in weak inversion

    Page(s): 12 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    This paper describes a voltage reference circuit based on composite transistors and operating in weak inversion mode. The voltage reference was fixed in 100mV and the supply voltage can be as low as 0.8V. The weak inversion allows small current too leading the total power in the nW range. Simulation results points to a deviation (3σ and process corner) less than ±1%. The reference is indicated to be used in biomedical applications specially those that use implanted devices. In these cases the temperature impact is minimized since the human body has an effective biological system to keep it constant at about 37°C. View full abstract»

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  • Low power CMOS potentiostat for three electrodes amperometric chemical sensor

    Page(s): 15 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (551 KB) |  | HTML iconHTML  

    This paper presents two front-end electronics architectures, called potentiostats, developed for measuring gas concentrations with electro-chemical sensors. These potentiostats are designed to be integrated in wireless embedded systems. Consequently, the total power consumption is critical. An amperometric three-electrodes electro-chemical sensor has been chosen since it is powerless. Its electrical model has been determined in order to optimize the readout electronics associated. Two potentiostats have been realized in a 0.35μm CMOS process. The most power consumption optimized architecture designed in this work presents a consumption of 10.8μW over a range of detection included from 70nA to 25μA. View full abstract»

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  • A 0.7-V rail-to-rail buffer amplifier with double-gate MOSFETs

    Page(s): 19 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    This paper proposes a 0.7-V rail-to-rail amplifier with double-gate MOSFETs, which are possible candidates for CMOS technology nodes beyond 22nm. The back-gate of the input transistors are used to keep them on, which allows the inputs at the front gates to be varied from rail to rail. Unlike conventional rail-to-rail architectures, which require two differential pairs to achieve rail-to-rail input common-mode range, the unique properties of the double-gate transistor allow only one input differential pair to be used, thus making this a first rail-to-rail amplifier of its kind. The amplifier achieves a dc open-loop gain of 88 dB, a unity-gain frequency of 28 MHz with a phase margin of 63° at a load capacitance of 10 pF, and a dc power consumption of 80 μW. View full abstract»

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  • Low power and fast adder implementation with Double Gate MOSFETs

    Page(s): 23 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB) |  | HTML iconHTML  

    In this paper we present implementation of a 32-bit adder using Quad Carry Look Ahead(QCLA) algorithm in compound domino logic with Merged Pre-charge Keeper transistor and Statistically Skewed Inverter with Double Gate MOSFET(DGMOSFET)s. The worst case propagation delay of the adder is 220ps. The average operating power is 186 μW. View full abstract»

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  • Ring oscillators: The asynchronous alternative

    Page(s): 27 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1110 KB) |  | HTML iconHTML  

    Self-timed rings (STR) are promising approach for designing high-speed serial links and clock generators. Indeed, the architecture of STRs presents well-suited characteristics for managing process variability and offering an appropriate structure to limit the phase noise. Therefore, STRs are considered as promising solution for generating Multiphase clocks. Moreover, Self-Timed Rings can easily be configured to change their frequency by controlling their initialization at reset time. A test chip has been designed and fabricated in STMicroelectonics CMOS65nm technology to verify the theoretical claims and validate the simulation results. View full abstract»

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  • Passive sensors network for temperature detection

    Page(s): 31 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    The dissipation of energy by the electronic signal conditioning is considered one of the essential issues to which network designers of microsensor have to face. With the aim of achieving significant reduction in energy consumption, we validate in this paper the use of a newly developed temperature sensor to enable us to perform wireless temperature measurement without using power. View full abstract»

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  • Application-based workload model for wireless sensor node computing platforms

    Page(s): 35 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB) |  | HTML iconHTML  

    Wireless sensor node platforms are very diversified and very constrained, particularly in power consumption. When choosing or sizing a platform for a given application, it is necessary to be able to evaluate in an early design stage the impact of those choices. Applied to the computing platform implemented on the sensor node, it requires a good understanding of the workload it must perform. Nevertheless, this workload is highly application-dependent. It depends on the data sampling frequency together with application-specific data processing and management. It is thus necessary to have a model that can represent the workload of applications with various needs and characteristics. In this paper, we propose a workload model for wireless sensor node computing platforms. This model is based on a synthetic application that models the different computational tasks that the computing platform will perform to process sensor data. It allows to model the workload of various different applications by tuning data sampling rate and processing. A case study is performed by modeling different applications and by showing how it can be used for workload characterization. View full abstract»

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  • New approach for application architecture adequacy in hardware/software embedded system design

    Page(s): 39 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB) |  | HTML iconHTML  

    This paper deals with a new approach to minimize the gap between application development and the architecture synthesis, in the hardware/software embedded system design flow. Indeed, two intermediate models are proposed, the analytic Hmodel, and the MACBuilder environment. The first one allows embedded system modelling with a state space approach in order to determine the recursive equations, whereas, the second one builds a set of task graph that models the system functionalities. Further, this paper investigates how a similar approach can be applied to improve the controller architecture design through a case study. View full abstract»

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  • Simulation tool for microsensor design driven by autonomy constraints

    Page(s): 43 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    In this article, we propose a simulation tool based on a system level modeling of microsensor nodes. This tool aims to compare different node architectures from hardware and software points of views in order to satisfy specifications of a Wireless Sensor Network including the autonomy constraint. As a result, it enables to choose an energy source including energy harvesting solutions and to select the best configuration for the node components. View full abstract»

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  • Fast electrical battery model builder for embedded systems

    Page(s): 47 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8402 KB) |  | HTML iconHTML  

    When designing embedded systems, industries need to correctly size the battery to guarantee the autonomy and the lifetime required for their application. However, for battery behavior simulation, there is often a lack of accurate and realistic models. To help efficiently the system designer, we propose a strategy in three steps: first by guiding the cell technology choice, second by calibrating battery size and third by proposing a methodology to build an electrical battery model. To obtain such a model rapidly, we have realized a Battery Model Builder (BMB) that automatically reads measurements and builds the model for variable temperature. The resulting model can be used to verify battery sizing or can be integrated for energy estimations of the whole system. View full abstract»

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  • Data coding methods for low-power aided design of submicron interconnects

    Page(s): 51 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    We present in this paper a CAD tool that aims at designing low-energy buses. The Graphical User Interface (GUI) we developed manages many techniques dealing with the addressed problem: simple coding, coding subject to fixed / dynamic probabilities and an enhanced dynamic probabilities- based technique. Moreover, this environment allows tuning the parameters of data encoding / decoding and is able to generate different gains by varying the size of the bus transferring the encoded data. Thus, this tool is suitable for efficiently designing telecommunication and multimedia systems that are strong data consumers and can be easily configured to integrate new coding techniques, then using one of them when favorably compared against the other techniques. View full abstract»

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  • Embedding functional simulators in compilers for debugging and profiling

    Page(s): 55 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    In embedded systems, achieving good performances for signal processing applications is crucial for power management. Good compilation is required to have maximal use of the available processing capabilities. Compiling for communication-exposed architectures such as ADRES, TRIPS and Wavescalar is however a complex task. Dataflow graphs are mapped on execution unit grids in order to increase the instruction-level parallelism while minimizing communication. Complex algorithms and the large number of code optimizations make debugging hard for the developer. Moreover, iterative approaches are used to optimize the compiled code quality. This paper proposes to embed functional simulators in compilers in order to enable debugging and profiling-driven iterative compilation. Debugging of optimization passes is achieved by means of functional simulators, running the original code and the transformed code. Intermediate and output values results comparison allows to verify the correctness of the optimization pass. Using embedded simulators also allows to extract code and execution characteristics convenient for iterative compilation. We present the mechanisms required to control those simulators. A case study based on the TRIPS processor demonstrates the usefulness of our approach. View full abstract»

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  • Beyond 3G wideband and high linearity ADCs

    Page(s): 59 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    This paper presents the challenges associated to the design of ADCs which must be compliant with 4G/LTE/LTE-A radio requirements. Primarily, the challenges are caused by increasing spectrum bandwidth, multi mode operation and the need of limiting the power consumption in the handset and in the base station. Therefore, wideband converters with high linearity (up to 100 dB of SFDR) and low power consumption (down to 0.5pJ by conversion step) are searched out with possibilities of reconfiguration to deal with the inherent trade-off between all these achievements. The paper gives an overview of the most common ADC architectures to achieve this goal: Flash, Pipeline, Successive Approximation and Sigma Delta ADCs. Then, efficient or still promising techniques are proposed to enhance performance. These techniques are mainly architectural innovations such as continuous time ΣΔ modulators and parallel architectures. The analog circuitry linearity tends to decrease due to the use of new advanced technologies, of increased speed and of simplification dictated by the need of power consumption reduction. However, an increasing use of calibration and digital correction allows both to compensate for the accuracy losses in analog circuitry and to reach higher performance. View full abstract»

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  • Low power and fast DCT architecture using multiplier-less method

    Page(s): 63 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    In this paper, a low power and fast DCT (Discrete Cosine Transform) using multiplier-less method is presented with a new modified FGA (Flow-Graph Algorithm), which is derived from our previously presented FGA of DCT based on Loeffler algorithm. The multiplier-less method is based on the replacement of multiplications with a minimum number of additions and shifts. The proposed FGA is performed and compared to a previous one. The results of FPGA implementations on Altera Cyclone II show the increase of the maximum frequency, the decrease of the resources usage and the reduction of the dynamic power by 7.2 % at 120 MHz of clock frequency with a new proposed FGA algorithm. Another comparison with recent published results has been done and proves the efficiency of the proposed FGA. View full abstract»

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  • Multiple threshold voltage for glitch power reduction

    Page(s): 67 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    We address the problem of circuit-level design for low power. We describe a new method for glitch power reduction based on threshold voltage adjustment. The proposed method achieves both dynamic and leakage power reductions. We develop an optimization algorithm that optimizes the circuit netlist to achieve glitch energy reductions without affecting the overall circuit delay requirement. Applying the algorithm to C17 benchmark circuit implemented in a 65nm industrial Low Power CMOS process, we have achieved 14% total energy savings and 78% leakage energy savings at the expense of just 5% delay increase. View full abstract»

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  • 173nA-7.5ppm/°C-771mV-0.03mm2 CMOS resistorless voltage reference

    Page(s): 71 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from -40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2. View full abstract»

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  • Evolution of wireless sensor networks and necessity of power management technique

    Page(s): 75 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (717 KB) |  | HTML iconHTML  

    Wireless sensor networks interfere in a growing number of applications ranging from simple environmental monitoring like temperature detection to complex calculation such as video processing. This last type of application requires a high load at the sensor level and leads to a problem of optimization. It is critical to design algorithms and protocols in such a way to use minimal energy. This paper provides a survey of WSNs technologies, main applications and hardware evolutions. In the other hand, we will provide an insight about the latest trends of the technique to reduce the power consumption within the WSN that could possibly make this emerging technological area more useful than ever. View full abstract»

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  • An ultra low power analogue radial basis function Network

    Page(s): 79 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB) |  | HTML iconHTML  

    This paper provides the circuits which are needed to implement RBF Neural Networks. A novel circuit to implement an M-dimensional Euclidean distance is presented. All the blocks were designed in weak inversion region to gain ultra low power consumption. The results were done using HSPICE by level 49 parameters (BSIM3v3) in 0.35μm standard CMOS technology. Finally, an RBF neuron with five hidden layers to approximate a nonlinear function is implemented. Having confirmed that the proposed circuit is working properly, simulation results have shown that the power consumption of our circuits is about several microwatts. View full abstract»

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  • A band pass Auto-Zeroing Floating-Gate Amplifier

    Page(s): 83 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    In this paper we present a band pass Auto-Zeroing Floating-Gate Amplifier (AZFA). The amplifier is based on Pseudo Floating gate and in addition to gain, it offers frequency band adjustment. Both the low-frequency and high-frequency cutoffs are controlled electronically, thus the amplifier can be used in design of various time continues filters. The AZA enjoys low component spread and compactness, containing only small size transistors and capacitors. View full abstract»

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