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Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

5-7 Oct. 1998

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  • Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

    Publication Year: 1998
    Request permission for commercial reuse | PDF file iconPDF (572 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s):642 - 643
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    Freely Available from IEEE
  • Performance-driven board-level routing for FPGA-based logic emulation

    Publication Year: 1998, Page(s):199 - 201
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    Previously, two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-le... View full abstract»

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  • Model checking of a real ATM switch

    Publication Year: 1998, Page(s):195 - 198
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    In this paper we present our experience on model checking of an Asynchronous Transfer Mode (ATM) switch using the Verification Interacting with Synthesis (VIS) tool. The switch we considered is in use for real applications in the Cambridge Fairisle network. It is composed of four input/output port controllers and a switch fabric, and contains around 1 MB memory, 2 KB FIFO buffer and 800 registers ... View full abstract»

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  • Automatic data path abstraction for verification of large scale designs

    Publication Year: 1998, Page(s):192 - 194
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    The state space explosion problem is a hurdle in the acceptance of model checking as a viable tool for verification of large-scale designs. Abstractions may be used to simplify designs, while preserving target verification properties. We propose a simple methodology for abstracting away portions of the data path, thus rendering a large state-space model of the design amenable for verification usin... View full abstract»

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  • Scheduling under data and control dependencies for heterogeneous architectures

    Publication Year: 1998, Page(s):602 - 608
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    This paper presents a list-scheduling algorithm for graphs with data and control dependencies. We assume that tasks are partitioned between hardware resources as scheduling takes place after partitioning in our co-synthesis tool. Control dependencies are introduced by if statements, and model complementary functionalities. A detailed discussion of our algorithm is presented. Extensive experimental... View full abstract»

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  • Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus

    Publication Year: 1998, Page(s):414 - 419
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    The energy at the I/O pins is a significant part of the overall consumption of a chip. To reduce this energy, this work extends to the data bus the working zone encoding method originally applied to encoding an external address bus. This method is based on the conjecture that programs favor a few working zones of their address space at each instant and that addresses to consecutive accesses for ea... View full abstract»

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  • Methods for calculating coupling noise in early design: a comparative analysis

    Publication Year: 1998, Page(s):76 - 81
    Cited by:  Papers (14)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    In this paper we compare different methods for calculating coupling noise, specially for use in the early design phase of a high performance custom design when all the detailed physical design information is not available. This analysis can be important in the design of functional blocks such as data paths in microprocessors, where if noise avoidance is included in the design planning phase, later... View full abstract»

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  • The Microcore development system: a unified environment for designing new microprocessors

    Publication Year: 1998, Page(s):190 - 191
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    This paper presents our methodology for designing new microprocessor architectures. We have developed a complete set of tools to simplify the debugging tasks within the design flow. Starting with the specification followed by the implementation and finally the engineering test the designers work in a uniform environment where the configuration can be fully reused for each phase of the design View full abstract»

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  • Buffer size driven partitioning for HW/SW co-design

    Publication Year: 1998, Page(s):596 - 601
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    Partitioning is a very important task in hardware/software co-design. Generally the size of the edge cut-set is used to evaluate the communication cost. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning a... View full abstract»

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  • Timing analysis of combinational circuits containing complex gates

    Publication Year: 1998, Page(s):407 - 412
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    Current timing analysis tools deal with combinational circuit composed of primitive gates. In this paper, we are investigating ways to do timing analysis of combinational circuits with complex gates. Two possible approaches are proposed. The first approach is to design path sensitization criterion for circuits which is composed of complex gates. Another approach is first to transform complex gates... View full abstract»

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  • On short circuit power estimation of CMOS inverters

    Publication Year: 1998, Page(s):70 - 75
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Traditional power optimization and estimation techniques for digital CMOS circuits have focused on the dynamic power dissipation, caused by charging and discharging the load capacitances at the gate outputs. However, as the device size and threshold voltage continue to decrease, the short circuit power dissipation is no longer a negligible factor. We show that previously published models for the s... View full abstract»

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  • Adaptive synchronization

    Publication Year: 1998, Page(s):188 - 189
    Cited by:  Papers (15)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-synchronous hierarchical clocking provides the same frequency to all modules, but does not maintain any particular phase. Adaptive synchronizers... View full abstract»

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  • Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications

    Publication Year: 1998, Page(s):482 - 487
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    The instruction set and architecture of a SIMD processor optimized for real-time digital signal processing applications is presented. A novel structure allows computation and data I/O to be performed in parallel, provides interprocessor communications and enables the cascade of multiple chips without glue-logic to provide systems with large numbers of processors. Powerful processing elements and i... View full abstract»

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  • Current-based testing for analog and mixed-signal circuits

    Publication Year: 1998, Page(s):576 - 581
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    A new test technique for analog and mixed-signal circuits which employs current signals as input test stimuli is presented in this paper. With the current-based test technique proposed, it is possible to simplify test stimulus generation, minimize the probability of erroneous test decisions and maximize fault coverage. In addition, this technique has significant advantages for DFT and BIST impleme... View full abstract»

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  • Dynamic fault diagnosis for sequential circuits on reconfigurable hardware

    Publication Year: 1998, Page(s):214 - 215
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In this paper, we introduce a new approach for locating and diagnosing faults in sequential circuits. The approach is based on automatically designing a circuit which implements a closest match fault location algorithm specialized for the sequential circuit under diagnosis. Our result shows an order of magnitude improvements in term of speeds over software based fault location View full abstract»

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  • AMULET3: a high-performance self-timed ARM microprocessor

    Publication Year: 1998, Page(s):247 - 252
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    AMULET3 is a fully asynchronous implementation of ARM architecture v4T and was designed at the University of Manchester between 1996 and 1998. It is the third generation asynchronous ARM, and is aimed at a significantly higher performance level than its predecessors. Achieving this higher performance has required significant enhancements to the internal micro-architecture, such as the introduction... View full abstract»

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  • Data cache parameter measurements

    Publication Year: 1998, Page(s):376 - 383
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    We extend prior research by Saavedra and Smith on designing microbenchmarks to measure data cache parameters. Unlike Saavedra and Smith, we measure the parameters by characterizing read accesses separately from write accesses; and we do not assume that the address mapping function is a bit-selection. We can measure the cache capacity C, block size b, and associativity a; we can measure the cache-h... View full abstract»

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  • Software power estimation and optimization for high performance, 32-bit embedded processors

    Publication Year: 1998, Page(s):328 - 333
    Cited by:  Papers (70)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    A software energy estimation model is presented for a family of high performance, integrated, 32-bit embedded RISC processors. This model is significantly less complex than previous models, and yet is demonstrated to accurately predict energy consumption to within 8% with 99% confidence based on physical measurements. Factors such as operating frequency, source/destination registers, and operand v... View full abstract»

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  • Learning as applied to stochastic optimization for standard cell placement

    Publication Year: 1998, Page(s):622 - 627
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    Although becoming increasingly important, stochastic algorithms are often slow since a large number of random design perturbations are required to achieve an acceptable result-they have no built-in “intelligence”. In this work, we used regression to learn the swap evaluation function while simulated annealing is applied to 2D standard-cell placement problem. The learned evaluation func... View full abstract»

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  • Fast low-power shared division and square-root architecture

    Publication Year: 1998, Page(s):128 - 135
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    This paper addresses a fast low-power implementation of a shared division and square-root architecture. Two approaches are considered in this paper; these include the SRT (Sweeney, Robertson and Tocher) approach which does not require prescaling and the GST (generalized Svoboda and Tung) approach which requires prescaling of the operands. This paper makes two important contributions. Although SRT ... View full abstract»

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  • A self-timed real-time sorting network

    Publication Year: 1998, Page(s):427 - 434
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    High speed networks are expected to carry traffic classes with diverse Quality of Service (QoS) guarantees. For efficient utilization of resources, sophisticated scheduling protocols are needed; however; these must be implemented without sacrificing the maximum possible bandwidth. This paper presents the architecture and implementation of a self-timed real-time sorting network to be used in packet... View full abstract»

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  • Timing-driven routing for symmetrical-array-based FPGAs

    Publication Year: 1998, Page(s):628 - 633
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    In this paper, we present a timing-driven global router for symmetrical-array-based FPGAs. The routing resources in the symmetrical-array-based FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, traditional measure of routing delay based on ... View full abstract»

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  • Circuit design techniques for a gigahertz integer microprocessor

    Publication Year: 1998, Page(s):11 - 16
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology employed in this design. Particular attention was paid in the design process to the trade-off between performance and noise-margins. To achieve the... View full abstract»

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  • Clock-skew constrained placement for row based designs

    Publication Year: 1998, Page(s):219 - 220
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    In this paper we address the problem of placement of standard cells under the constraints of minimizing the clock-skew. We propose a quadratic programming based methodology for placement that not only results in an area and timing wise good placement but also a supporting zero-skew clock routing tree. Under the clock-skew constraints, our method produces significant reduction in the cost of zero-s... View full abstract»

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