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Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

5-7 Oct. 1998

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  • Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

    Publication Year: 1998
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    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s):642 - 643
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    Freely Available from IEEE
  • Clock-skew constrained placement for row based designs

    Publication Year: 1998, Page(s):219 - 220
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    In this paper we address the problem of placement of standard cells under the constraints of minimizing the clock-skew. We propose a quadratic programming based methodology for placement that not only results in an area and timing wise good placement but also a supporting zero-skew clock routing tree. Under the clock-skew constraints, our method produces significant reduction in the cost of zero-s... View full abstract»

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  • Methods for calculating coupling noise in early design: a comparative analysis

    Publication Year: 1998, Page(s):76 - 81
    Cited by:  Papers (14)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    In this paper we compare different methods for calculating coupling noise, specially for use in the early design phase of a high performance custom design when all the detailed physical design information is not available. This analysis can be important in the design of functional blocks such as data paths in microprocessors, where if noise avoidance is included in the design planning phase, later... View full abstract»

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  • Fault-tolerant architecture for high performance embedded system applications

    Publication Year: 1998, Page(s):384 - 389
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    The architecture of a fault-tolerant embedded computer system is presented. It employs multiple processors for high performance and dual-port memory units for interprocessor communication. The high performance embedded computer (HPEC) system consists of five processors that are partitioned into two sets namely the computing and IO partitions. The computing partition is concerned with computational... View full abstract»

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  • Learning as applied to stochastic optimization for standard cell placement

    Publication Year: 1998, Page(s):622 - 627
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB)

    Although becoming increasingly important, stochastic algorithms are often slow since a large number of random design perturbations are required to achieve an acceptable result-they have no built-in “intelligence”. In this work, we used regression to learn the swap evaluation function while simulated annealing is applied to 2D standard-cell placement problem. The learned evaluation func... View full abstract»

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  • A 690 ps read-access latency register file for a GHz integer microprocessor

    Publication Year: 1998, Page(s):6 - 10
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    This paper describes a 690 ps read-access latency, 32 entry by 64 bit, 3 read-port, 2 write-port, register file with internal bypass. The register file has been fabricated as a pan of 1.0 GHz single-issue 64-bit PowerPC integer processor. Fabrication technology was IBM CMOS6X: 0.25-μm drawn channel length, six-metal-layer (Al), 1.8 V nom. VDD. Self-resetting custom dynamic circuits a... View full abstract»

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  • VEGA: a verification tool based on genetic algorithms

    Publication Year: 1998, Page(s):321 - 326
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB)

    While modern state-of-the-art optimization techniques can handle designs with up to hundreds of flip-flops, equivalence verification is still a challenging task in many industrial design flows. This paper presents a new verification methodology that, while sacrificing exactness, is able to handle larger circuits and give designers the opportunity to trade off CPU time with confidence on the result... View full abstract»

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  • New compact representation of multiple-valued functions, relations, and non-deterministic state machines

    Publication Year: 1998, Page(s):168 - 174
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    In this paper we present a new data structure for representing multiple-valued relations (functions in particular) both completely and incompletely specified. The same format can be used for non-deterministic state machines (deterministic in particular). Relations are represented by labeled rough partitions, a structure similar to rough partitions, but storing the full information about relations ... View full abstract»

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  • On thin Boolean functions and related optimum OBDD ordering

    Publication Year: 1998, Page(s):216 - 218
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    This paper investigates the optimum OBDD representation problem based on two classes of Boolean functions. The first class is defined by OBDDs, in which the number of non-terminal nodes is equal to the number of input variables. We refer to such OBDDs and their corresponding Boolean functions as thin OBDDs and thin Boolean functions. The second class is the thin factored Boolean functions, which i... View full abstract»

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  • Partitioning in time: a paradigm for reconfigurable computing

    Publication Year: 1998, Page(s):340 - 345
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    In recent years, we have witnessed the rapid growth of reconfigurable computers. The first generation of reconfigurable computers consists of multiple FPGAs interconnected in a network. The computations are performed by partitioning an entire task into spatially interconnected sub-tasks. FPGAs used in the reconfigurable computers are programmed only once during the runtime of an executing applicat... View full abstract»

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  • On short circuit power estimation of CMOS inverters

    Publication Year: 1998, Page(s):70 - 75
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Traditional power optimization and estimation techniques for digital CMOS circuits have focused on the dynamic power dissipation, caused by charging and discharging the load capacitances at the gate outputs. However, as the device size and threshold voltage continue to decrease, the short circuit power dissipation is no longer a negligible factor. We show that previously published models for the s... View full abstract»

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  • Data cache parameter measurements

    Publication Year: 1998, Page(s):376 - 383
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    We extend prior research by Saavedra and Smith on designing microbenchmarks to measure data cache parameters. Unlike Saavedra and Smith, we measure the parameters by characterizing read accesses separately from write accesses; and we do not assume that the address mapping function is a bit-selection. We can measure the cache capacity C, block size b, and associativity a; we can measure the cache-h... View full abstract»

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  • DCP: an algorithm for datapath/control partitioning of synthesizable RTL models

    Publication Year: 1998, Page(s):442 - 449
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Currently, the majority of ASIC and custom chip implementations go through a process by which a cycle-accurate synthesizable RTL model is refined into an RT/gate-level model that has been partitioned into datapath and control. This partitioning is usually done manually. This paper describes an algorithm for automatic datapath/control decomposition of synthesizable RTL models based on communication... View full abstract»

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  • Combining technology mapping with post-placement resynthesis for performance optimization

    Publication Year: 1998, Page(s):616 - 621
    Cited by:  Papers (6)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    This paper presents an innovative two-phase approach which combines technology mapping with logic resynthesis for minimizing the post-placement delays. The main idea is to alleviate the effect of inaccurate delay models in the mapping phase and to use a more accurate post-placement delay model in the logic resynthesis phase. To achieve this, our mapping phase disables the operations which may prov... View full abstract»

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  • Automatic data path abstraction for verification of large scale designs

    Publication Year: 1998, Page(s):192 - 194
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    The state space explosion problem is a hurdle in the acceptance of model checking as a viable tool for verification of large-scale designs. Abstractions may be used to simplify designs, while preserving target verification properties. We propose a simple methodology for abstracting away portions of the data path, thus rendering a large state-space model of the design amenable for verification usin... View full abstract»

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  • A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics

    Publication Year: 1998, Page(s):286 - 291
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    One of the most successful algorithms that bring realism to the world of 3D-image generation is Phong shading. But, Gouraud shading has been used instead of Phong shading because of per pixel computation and hardware costs. However, with continuous improvement of VLSI technologies and request for higher realism, real-time Phong shading will be the next technology-push in 3D graphics. Taylor series... View full abstract»

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  • Timing analysis of combinational circuits containing complex gates

    Publication Year: 1998, Page(s):407 - 412
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    Current timing analysis tools deal with combinational circuit composed of primitive gates. In this paper, we are investigating ways to do timing analysis of combinational circuits with complex gates. Two possible approaches are proposed. The first approach is to design path sensitization criterion for circuits which is composed of complex gates. Another approach is first to transform complex gates... View full abstract»

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  • Silicon microsystems merging sensors, circuits and systems

    Publication Year: 1998, Page(s):634 - 641
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    While the electronic properties of silicon are widely utilized in high-volume IC manufacturing, the use of its mechanical as well as its other properties is still lagging behind. Recent advances in IC-compatible micro-machining techniques, however, have created the technological basis for constructing miniature, high-precision, mechanical structures in and on silicon. Thus microsensors and microac... View full abstract»

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  • To model check or not to model check

    Publication Year: 1998, Page(s):314 - 320
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    In the past, hardware design validation has relied primarily on simulation. New techniques such as model checking have been introduced but no objective study investigating the advantages such techniques provide over simulation has been made. Simulation is model checking over a trace elicited by executing a test vector; model checking can be viewed as exhaustive simulation. Each has its own set of ... View full abstract»

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  • On finding undetectable and redundant faults in synchronous sequential circuits

    Publication Year: 1998, Page(s):498 - 503
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    We describe a time-efficient procedure for identifying undetectable and redundant faults in a synchronous sequential circuit, without using a sequential circuit test pattern generator. The proposed procedure is based on the use of a limited length iterative logic array model of the circuit, and has two phases. In the first phase, faults that will not be proved to be undetectable are identified. In... View full abstract»

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  • Area-oriented synthesis for pass-transistor logic

    Publication Year: 1998, Page(s):160 - 167
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    Pass Transistor Logic (PTL) circuits have been successfully used to implement digital ICs which are smaller, faster, and more energy efficient than static CMOS implementations of the same designs. Thus far, most PTL implementations have been handcrafted; as such, designer acceptance of PTL has been limited. In this paper, we develop efficient algorithms for automated synthesis of high quality PTL ... View full abstract»

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  • Dynamic fault diagnosis for sequential circuits on reconfigurable hardware

    Publication Year: 1998, Page(s):214 - 215
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In this paper, we introduce a new approach for locating and diagnosing faults in sequential circuits. The approach is based on automatically designing a circuit which implements a closest match fault location algorithm specialized for the sequential circuit under diagnosis. Our result shows an order of magnitude improvements in term of speeds over software based fault location View full abstract»

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  • System-level performance estimation strategy for sw and hw

    Publication Year: 1998, Page(s):48 - 53
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    The design of an embedded system is a process where the tuning of the architecture should take into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling... View full abstract»

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  • The Alpha 21264 microprocessor architecture

    Publication Year: 1998, Page(s):90 - 95
    Cited by:  Papers (76)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    The 21264 is the third generation Alpha microprocessor from Compaq Computer (formerly Digital Equipment) Corporation. This microprocessor achieves the industry-leading performance levels of 30+ Specint95 and 50+ Specfp95. In addition to the aggressive 600 MHz cycle time in a 0.35 μm CMOS process, there are also many architectural features that enable the outstanding performance level of the 212... View full abstract»

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