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Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st

Date May 31 2011-June 3 2011

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Displaying Results 1 - 25 of 350
  • Foreword

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  • Best of conference papers - 2010

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  • Committee members

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  • Table of contents

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  • Affiliation index

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  • Author index

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  • [Copyright notice]

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  • Looking for research results in components, materials, modeling, packaging, reliability and the other fields covered at ECTC?

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  • Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

    Page(s): 1 - 6
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    This paper presents on a novel chip-to-wafer (C2W) three-dimensional (3D) integration technology with well-controlled template alignment and wafer-level bonding, enabling precise alignment, few thermal cycles and high throughput of 3D system fabrication. The key processes are investigated and discussed in detail, including chip edge definition, template fabrication, C2W alignment and wafer-level bonding. The C2W 3D integration technology is successfully demonstrated using Cu daisy chains, a patterned thick benzocyclobutene (BCB) layer on the wafer as the alignment template, and wafer-level C2W Cu-Cu bonding. An alignment accuracy less than 2 μm is achieved. The FIB-SEM images reveal that Cu grains cross the original Cu-Cu bonding interface to form strong bonding. The measured I-V characteristics of daisy chains show a linear ohmic behavior, and the specific contact resistance of Cu-Cu bonding structures is on the order of 10-8 ohm-cm2, suggesting good electric contacts. View full abstract»

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  • Fluxless bonding for fine-pitch and low-volume solder 3-D interconnections

    Page(s): 7 - 13
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    Fluxless bonding can be used for fine-pitch low-solder-volume interconnections for three-dimensional large-scale integrated-circuit (3D-LSI) applications. Surface treatments with hydrogen radicals, formic acid, vacuum ultraviolet (VUV), and Ar plasma were evaluated as candidate methods for fluxless bonding. Three-μm-thick Sn solders were evaluated for intermetallic-compound (IMC) bonding of 3D integration as a target material for fluxless bonding. X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), time-of-flight secondary ion mass spectrometry (TOF-SIMS), a scanning electron microscope (SEM), and a focused ion beam scanning ion microscope (FIB-SIM) were used to examine the samples. The experiments shows solder oxides and organic contaminants on the surfaces of the micro-bumps were most effectively eliminated without flux by hydrogen radical treatment among various treatments we evaluated. Bonding strength was also improved by the hydrogen radical treatment, since the shear strength was more than 50 times stronger than that of the untreated samples. View full abstract»

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  • Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

    Page(s): 14 - 21
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    3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200 mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10-4 A/cm2 at an - - ambient temperature of 150°C. View full abstract»

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  • Thermal reliability of fine pitch Cu-Cu bonding with self assembled monolayer (SAM) passivation for Wafer-on-Wafer 3D-Stacking

    Page(s): 22 - 26
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    Three-dimensional integrated circuit (3D IC) is a technology that has the potential to overcome conventional scaling limits by reducing signal propagation delay and power consumption. Wafer-on-Wafer 3D-Stacking is a more practical option for high throughput manufacturing of 3D IC. It is important to ensure excellent electrical, mechanical and thermal properties of the bonding interface for robustness and long term reliability. Cu-Cu bonding has advantage in terms of excellent scalability which enables fine pitch vertical interconnect formation, providing a promising technique to meet future high density 3D IC requirement. In this work, we study the improvement in the contact resistance of the bonded Cu-Cu contacts with self-assembled monolayer (SAM) passivation prior to bonding and the thermal endurance of these contacts. A reduction of ~7.1% in the contact resistance is observed with the application of SAM for bonding at 350°C. We further show that SAM passivation is extendible to the formation of high density fine-pitch Cu-Cu bonding with 100% bonding yield that sustains extreme thermal cycling. View full abstract»

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  • High density 20μm pitch CuSn microbump process for high-end 3D applications

    Page(s): 27 - 31
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    In this paper, we present a high yielding 20μm pitch CuSn electroplated microbump flip chip process. The 10μm diameter bumps are organized in an area array, consisting of 440 daisy chains of 1766 bumps each. The 2cm × 2cm flip-chipped dies consist of about 1M bumps in total. The influence of processing materials like seed layer etchants and cleaning agents on the electrical performance of the daisy chains is discussed. Further Ti/Cu versus TiW/Cu seed layers for electroplating are compared. Finally inspection methods for tracing back electrically measured failures are screened. View full abstract»

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  • Homo/heterogeneous bonding of Cu, SiO2, and polyimide by low temperature vapor-assisted surface activation method

    Page(s): 32 - 36
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    This paper presents high feasibility of homo/heterogeneous bonding of Cu, SiO2, and polyimide by means of the vapor-assisted surface activation method at 150°C at atmospheric pressure. Such a bonding technology is expected to have high practical value when three-dimensional integration of thin and flexible bumpless structures, which are made of diverse materials including organic substrate, is considered, because the flattened surfaces of metal electrodes and insulation layer should be bonded at the same time for the sake of low process complexity. In order to obtain sufficient binding energy on the surfaces of mixed materials and a good electrical conduction at the metal-metal interface, a bridging layer that is applicative to metal, ionic-bond material, and polymeric material, has to be developed regardless of the difference in bond mechanisms. For Cu and SiO2, we created the bridging layers based on Cu hydroxide hydrate and silanol group, respectively, by introducing water vapor onto the atomically clean surfaces. With this process, it was proven that considerably low contact resistance was obtained at the Cu-Cu interface with a controlled layer thickness. This technique was considered effective also to the polyimide surface since an ultrathin layer of molecular-bound water would be available once the oxo anion in the main chain is dissociated and substituted with hydroxyl. Therefore, it was necessary to specify: 1) The condition of surface cleaning by the Ar fast atom beam (Ar-FAB); and, 2) The change in chemical binding state of the outmost surface through the adsorption of water molecules. We carried out the X-ray photoelectron spectroscopy (XPS) analyses for the polyimide surface as well as Cu and SiO2, after their atomically clean surfaces were exposed to nitrogen gas at different absolute humidity. The change in atomic concentration ratio taken from C1s, N1s and O1s spectra of polyimide indicated that the oxo anion w- - as removed preferentially during the beam bombardment rather than the ring opening at the main chain end. The angle-resolved and depth profiling results showed that the formation of hydroxyl, which would induce the adsorption of water molecules in ambient condition, occurred with the thickness increasing concomitantly with the number of water molecules in collision with the clean surface. In the bonding experiments, such hydrophilic surfaces were proven to make tight bridges with the surfaces of Cu and SiO2. Transmission electron microscopy (TEM) and electron energy-loss spectroscopy (EELS) analyses provided the results that nominally voidless interfaces were obtained in the combinations of polyimide-Cu, polyimide-SiO2, and Cu-Cu at 150°C through oxygen-rich amorphous bridging layers, when the absolute humidity was limited to 8 g/m3 to control the interfacial layer thickness to be less than 15 nm. View full abstract»

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  • High resolution acoustical imaging of high-density-interconnects for 3D-integration

    Page(s): 37 - 42
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    Due to increasing integration density, breakthrough improvements in the resolution achievable by a specific inspection method are of great interest to the 3D Integration community. This requirement is particularly driven by wafer bonding technologies that, in addition to mechanical 3D assembly, were also often used to form buried electrical chip-to chip interconnects with bonding pitch dimensions on the order of 10 μm. Acoustic microscopy is a unique tool for nondestructive inspection of internal structures in opaque materials. However, in acoustics the achievable resolution is strongly dependent on the wavelength of the insonated signal, which varies dramatically with the acoustic wave velocity. In the current study bonded devices with electrical routings in the bonded interface were inspected using acoustic microscopy applying highly focussed ultrasonic transducers with acoustic frequencies ranging from 100 MHz up to 1 GHz. Samples inspected contained high density interconnects (106 per cm2) forming large area arrays (512 × 640) on 10 μm and 15 μm pitch. Depending on the thickness of the top-layer the acoustic frequency and focal length of the transducer was selected for imaging. With a resolution of approx. 1 μm acoustic imaging of the metal-links behind 5 μm of BCB and underfill was performed. Delaminations of the lateral links were detected without opening the mounted polymer layer. The delaminated links were confirmed by FIB cross-sectioning and high-resolution SEM imaging. In addition voids in the underfill material (a low moisture absorption epoxy) have been detected through the top-die. In further experiments acoustic inspection of the interconnects between the two wafers have been performed at 100 MHz, 200 MHz and 400 MHz with focal lengths of 2 mm down to 200 μm. The trade-off between the achievable resolution, acoustic attenuation and the thickness of the top-die has to be take- - n into account when imaging at a 5 μm scale through opaque polymer materials. It is expected that semi-destructive preparation will be required in practical applications, namely thinning of the top-wafer to an appropriate thickness. However, for performing failure analysis the acoustic inspection of the interconnects and the detection of delaminations at the interfaces between the dielectrics, underfills and metals in the bonded devices will be greatly beneficial for guiding additional destructive imaging and analyses. View full abstract»

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  • Low cost, chip-last embedded ICs in thin organic cores

    Page(s): 43 - 47
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    This paper presents a novel technology to enable chip embedding in 1 or 2 metal layer substrates using chip-last embedding for its merits. The novel structure is obtained by embedding thin-chips within the core instead of the build-up layers as has been demonstrated previously [1]. To enable the smallest profile embedded die structure, results from the three critical elements of the technology- 1) fine lines and spaces on core, 2) small-diameter fine-pitch area-array through-holes, and 3) thermo-mechanical reliability of small diameter through-holes have been discussed in the paper. Lines and spaces as small as 7μm were demonstrated on core laminate by using build-up type processes. Copper-filled through-holes of 30-60μm diameters were successfully fabricated and shown to pass 1300 thermal cycles from -55°C to 125°C. In addition, through-hole drilling process was optimized to achieve ultra-fine pitches of 70-100μm. Comprehensive analysis of three new materials and associated fabrication processes, carried out to demonstrate the advantages and robustness of this manufacturing-friendly 1-2 metal layer chip-last embedding technology emphasizes that it is a promising technology to achieve ultra-miniaturization for future embedded systems and sub-systems. View full abstract»

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  • Through mold vias for stacking of mold embedded packages

    Page(s): 48 - 54
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    The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm2. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular moldi- - ng compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes. View full abstract»

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  • Embedded package wafer bow elimination techniques

    Page(s): 55 - 58
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    We outline several approaches to allow individual die to be encapsulated within a silicon substrate, which we define as a cavity wafer, without causing wafer bow. This technique forms the basis for a novel integrated ultra high density (i-UHD) wafer-level packaging platform. The iUHD process begins with a standard Si wafer that is patterned and dry etched to form cavities that accept buried components. After etching, the wafer is blanket metalized. Individual commercial off-the-shelf (COTS) die are placed onto an adhesive film and precision transferred to the substrate wafer. Low coefficient of thermal expansion (CTE) encapsulant is injected into the cavity surrounding the die. Finally, the adhesive film is removed to reveal a planar surface on the reconstructed core wafer. Multilayer interconnect is fabricated on both sides of the core using standard wafer fabrication techniques. A challenge to this approach has been that curing and shrinkage of the encapsulant, as well as its CTE mismatch with silicon, creates wafer bow. In this paper we present a technique that eliminates bow by mirroring the die-side wafer cavities about the neutral bending axis. View full abstract»

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  • System in wafer-level package technology with RDL-first process

    Page(s): 59 - 64
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    We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level. View full abstract»

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  • Lithography technique to reduce the alignment errors from die placement in fan-out wafer level packaging applications

    Page(s): 65 - 70
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    The rapid growth of wireless consumer electronics products is driving demand for cost effective and small form factor packaging solutions. While front end silicon technologies have followed Moore's law by device scaling, the back end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on silicon is significantly higher than the speed achieved on the printed circuit boards. Innovative advancements such as Fan-out wafer level packaging technology were introduced to address the pad limitation consideration with traditional wafer level packaging while delivering miniaturization and potential low cost packaging advantages. It does this by extending the package interconnect area beyond the front end chip size to allow increased number of I/O required for large die sizes. This technology allows tested-good dice to be reconstituted into wafer form, and interconnections are formed using wafer level processing technology. Die positioning control within the reconstituted wafer significantly affects downstream process requirements. The use of high productivity pick and place equipment with multiple gantries create challenges for the lithographic tool alignment when die placements from each gantry are not identical. This will be especially true in the future as the placement tolerances are reduced for advanced products containing multiple die types. This paper describes the inaccuracy in pick and place from single and dual gantry operation, and investigates lithographic alignment methods specifically developed to minimize pick and place errors from multiple gantry operation. The current single zone alignment algorithm was extended to create multiple selection zones to match the multiple gantries of the die pick and place equipment. The enhanced capability allows the flexibility to conduct a separate alignment mapping for different zones of the reconstituted Fan-out wafers. The dual zone mapping gave more effe- - ctive compensation for a gantry matching error, resulting in better than 50% improvement in registration error compared with a single zone mapping. This provides significantly superior alignment control for next generation devices fabricated with fan out wafer level packaging process. View full abstract»

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  • Reliability evaluation on low k wafer level packages

    Page(s): 71 - 77
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    Wafer Level Package (WLP) technology has seen tremendous advances in recent years and is rapidly being adopted at the 65 nm Low-K silicon node. For a true WLP, the package size is same as the die (silicon) size and the package is usually mounted directly on to the Printed Circuit Board (PCB). Board level reliability (BLR) is a bigger challenge on WLPs than the package level due to a larger CTE mismatch and difference in stiffness between silicon and the PCB. The BLR performance of the devices with Low-K dielectric silicon becomes even more challenging due to their fragile nature and lower mechanical strength. A post fab re-distribution layer (RDL) with polymer stack up provides a stress buffer resulting in an improved board level reliability performance. Drop shock (DS) and temperature cycling test (TCT) are the most commonly run tests in the industry to gauge the BLR performance of WLPs. While a superior drop performance is required for devices targeting mobile handset applications, achieving acceptable TCT performance on WLPs can become challenging at times. BLR performance of WLP is sensitive to design features such as die size, die aspect ratio, ball pattern and ball density etc. In this paper, 65nm WLPs with a post fab Cu RDL have been studied for package and board level reliability. Standard JEDEC conditions are applied during the reliability testing. Here, we present a detailed reliability evaluation on multiple WLP sizes and varying ball patterns. Die size ranging from 10 mm2 to 25 mm2 were studied along with variation in design features such as die aspect ratio and the ball density (fully populated and de-populated ball pattern). All test vehicles used the aforementioned 65nm fab node. View full abstract»

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  • Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs)

    Page(s): 78 - 83
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    In this paper, we focus how to overcome process challenges, such as die shift and warpage, and to fabricate thin embedded wafer level packages (EMWLPs) with 200 μm-thick eventually. The initial warpage of reconfigured wafer after post mold curing (PMC) was about 1.0 ~ 1.4 mm range. After PMC, the molded wafer was background to 200 μm thickness and redistribution layer (RDL) process was conducted on both front- and back-sides of the molded wafer sequentially. However, the warpage increased up to several mm during 1st RDL formation so that multi-RDLs process could not be performed due to the largely warped wafer. In order to overcome the large warpage issue, thick Si wafer was adopted as a carrier and the molded wafer was bonded on the Si carrier before RDL process. The measured warpage values decreased from several mm to about 500 μm during RDL process by using the Si carrier and two RDLs were fabricated on both sides of the molded wafer. Consequently, the fabrication of 200 μm-thick molded wafer for EMWLPs was successfully achieved. Three reliability tests (MSL3, HAST, and TC) were performed with singulated EMWLP modules and no failure was observed in the results of component level reliability. Furthermore, for in-depth understanding of the effects of MCs and carrier types on the die shift of the reconfigured wafer, the die shift values were measured on the molded wafers made of different MCs and different carriers as well. The experimental results are being compared with computational simulation and this can provide basic guidance of material selection and molding process. View full abstract»

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  • Minor alloying effects of Ni or Zn on microstructure and microhardness of Pb-free solders

    Page(s): 84 - 89
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    To form reliable Pb-free solder joints, minor alloying additions of Ni or Zn to Sn-rich solders have been recommended recently. Several beneficial effects of Ni or Zn minor alloying additions to Pb-free solders were reported to improve solder joint reliability. But the effects of Ni or Zn minor alloying additions on the bulk properties of solders are not systematically evaluated in light of understanding the electromigration or mechanical reliability of solder joints. Therefore, in this study, the minor alloying effects of Ni or Zn on the microstructure and microhardness in terms of Ni or Zn composition and cooling rate are investigated. The amounts of minor alloying elements investigated are in the range of 0.05-0.15 wt% for Ni, and 0.2-0.6wt% for Zn, which cover the reported composition ranges to enhance solder/UBM joint reliability. Three cooling rates are employed during solidification; 0.02°C/s (furnace-cooling), about 5°C/s (air-cooling), and 100°C/s or higher (quenching). The microstructure of Ni or Zn doped solders is evaluated in terms of composition, undercooling during solidification, and cooling rate. The phase diagram analysis is conducted to explain the microstructural variations. The microstructures of Ni or Zn doped solders are well correlated to their microhardness data. View full abstract»

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  • Solidification processes in the Sn-rich part of the SnCu system

    Page(s): 90 - 99
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    In this study SnCu solder spheres (Ø 270 μm, CR ~ 1 K/s) were investigated in order to verify the solidified microstructure according to the Sn-rich part of the SnCu phase diagram. The investigated alloys are Sn99.9, SnCu0.25, SnCu0.5, SnCu0.7, SnCu0.9, SnCu1.2, SnCu1.5, and SnCu3.0. In order to understand the solidification process, such aspects as morphology, grain structure and undercooling were analysed. The microstructure was investigated by optical microscopy, SEM and EDX. The undercooling was measured by DSC. It will be shown that small SnCu solder spheres solidify not only with commonly known β-Sn dendrites and fine Cu6Sn5 IMCs in the interdendritic spacing, but with specific and systematic changes in morphology, which depend on composition. The successive morphology transitions were found: from 1) fine Cu6Sn5 IMCs in β-Sn to 2) small β-Sn cells to 3) β-Sn cellular/dendritic to 4) fine Cu6Sn5 IMCs in β-Sn or undirected β-Sn cells. The area fraction of these different morphologies and the number of grain orientations were estimated from the cross-sections of about 20 solder spheres per composition. This allows a quantitative description of the microstructure and its compositional dependency. The results also show that the formation of large Cu6Sn5 IMCs provokes more grain orientations compared to SnCu solders solidified without large intermetallic phases. View full abstract»

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