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1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

10-10 Oct. 1998

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  • 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

    Publication Year: 1998
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  • Loop Scheduling Algorithm For Timing And Memory Operation Minimization With Register Constraint

    Publication Year: 1998, Page(s):579 - 588
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    First Page of the Article
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  • Author index

    Publication Year: 1998, Page(s): 609
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    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s):609 - 610
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    Freely Available from IEEE
  • A heterogeneous HW-SW architecture for hand-held multimedia terminals

    Publication Year: 1998, Page(s):113 - 122
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (694 KB)

    One of the key issues in the design of portable multimedia systems is to find a good balance between flexibility and high processing power on one side, and area and power efficiency of the implementation on the other side. Dedicated hardware for specific functions is good in terms of power efficiency, but with the variety in signal processing functionality to be supported by a multimedia terminal,... View full abstract»

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  • A 16-bit parallel MAC architecture for a multimedia RISC processor

    Publication Year: 1998, Page(s):103 - 112
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    This paper presents a parallel MAC (multiply-accumulation) architecture designed for DSP applications on a 200-MHz, 1.6-GOPS multimedia RISC processor. The datapath architecture of the processor is designed to realize parallel execution of a data transfer and SIMD parallel arithmetic operations. SIMD parallel 16-bit MAC instructions are introduced with a symmetric rounding scheme which maximizes t... View full abstract»

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  • A fixed-point multimedia DSP chip for portable multimedia services

    Publication Year: 1998, Page(s):94 - 102
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (547 KB)

    Existing multimedia processors having millions of transistors are not suitable for portable multimedia services and existing fixed-point DSP chips having fixed data formats are not appropriate for multimedia applications. This paper proposes a multimedia fixed-point DSP (MDSP) chip for portable multimedia services and its chip implementation. MDSP employs parallel processing techniques, such as SI... View full abstract»

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  • Design and implementation of low-power DCT chip for portable multimedia terminals

    Publication Year: 1998, Page(s):85 - 93
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (673 KB)

    This paper describes the design and implementation of a low power 2D DCT chip for portable multimedia terminals. The chip architecture based on direct 2D approach reduces computational complexity and the power dissipation can be reduced accordingly. In the implementation of the direct 2D algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is adopted. In the rea... View full abstract»

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  • An enhanced template matching algorithm and its chip implementation

    Publication Year: 1998, Page(s):162 - 171
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    This paper presents an enhanced template matching algorithm and its chip implementation. The proposed algorithm called the enhanced moment preserving pattern matching (EMPPM) improves the noise margin by 22% compared with the previously proposed algorithm called the moment preserving pattern matching (MPPM) algorithm. In addition, the proposed architecture can reduce the gate count by more than 28... View full abstract»

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  • An overlap-add free musical noise analysis-synthesis system

    Publication Year: 1998, Page(s):220 - 229
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (606 KB)

    An analysis-synthesis system for audio signals using sinusoidal model-based algorithms for harmonic component reconstruction and noise modeling for stochastic component synthesis has recently demonstrated the generation of high-quality synthetic signals. However current approaches, which mainly use phase randomization noise-driven source filter models with overlap-add techniques, have degraded the... View full abstract»

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  • Multiport memory and floating point Cordic pipeline in Jacobium processing elements

    Publication Year: 1998, Page(s):406 - 416
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    The Jacobium is a dataflow processor intended for high-speed execution of a set of algorithms that are akin to the so-called Jacobi method for reducing a symmetric matrix to diagonal form using Givens rotations. The design of this processor has been undertaken as one of two cases in a recently proposed method for the quantitative analysis of domain-specific dataflow architectures. The method presu... View full abstract»

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  • Protecting ownership rights of a lossless image coder through hierarchical watermarking

    Publication Year: 1998, Page(s):73 - 82
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (818 KB)

    Current market forces make it necessary for designers to protect their work against illicit use. Digital watermarks can be used to sign a design and thus establish ownership. We present a hierarchical set of techniques for intellectual property protection of a linear predictive image coder. Watermarking techniques employed include switching entries in the Huffman coding table, applying zero cost h... View full abstract»

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  • Field programmable DSP transform arrays

    Publication Year: 1998, Page(s):152 - 161
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (511 KB)

    Several dedicated VLSI architectures have been proposed in the literature for performing most of the linear transforms like DCT, DST, FFT and AFT, having orthogonal basis functions, though not much on the the non-orthogonal transforms like the Gabor. We present a hardware-reconfigurable architecture with which almost all these linear, nonlinear, orthogonal and non-orthogonal transforms can be perf... View full abstract»

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  • Multi-channel reverberation for computer music applications

    Publication Year: 1998, Page(s):210 - 219
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (627 KB)

    Reverberation is perhaps the most important post-production tool available to the sound engineer or computer musician. Geometrical methods are often used to model the acoustic properties of a room, including reverberation, but are limited to being valid only for high frequencies. At low frequencies, diffraction and the effects of room modes cannot be neglected. A method for modelling the two-dimen... View full abstract»

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  • A system-level reuse methodology for embedded data-dominated applications

    Publication Year: 1998, Page(s):551 - 560
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    This paper presents a system-level reuse methodology for data-dominated applications. A formalism is developed that structures the algorithmic specification in parts combining arithmetic and low-level control constructs that can be reused at the structural VHDL level without change and parts that combine the costly data-access-related constructs which are kept at higher levels in the code hierarch... View full abstract»

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  • Implementation of a DSSS modem ASIC chip for wireless LAN

    Publication Year: 1998, Page(s):243 - 252
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (563 KB)

    This paper presents a high-speed DSSS (direct sequence spread spectrum) modem ASIC chip for wireless local area network (WLAN). The implemented modem chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip supports various data rates, i.e., 4 Mbps, 2 Mbps and 1 Mbps and provides both DBPSK and DQPSK for data modulation. We have simulated algorithm models using the SPW View full abstract»

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  • A block-floating-point system for multiple datapath DSP

    Publication Year: 1998, Page(s):427 - 436
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    In order to give an answer to the question of the arithmetic representation in future DSP architectures for mobile communication applications, the signal processing quality of different arithmetic representations has been studied. Based on the result, an implementation of a novel block-floating multiple datapath DSP has been developed. This implementation allows a superior signal processing perfor... View full abstract»

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  • Input recoding for reducing power in distributed arithmetic

    Publication Year: 1998, Page(s):599 - 608
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (617 KB)

    Digital signal processing algorithms rely heavily on the efficient computation of inner products. Distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of precalculated partial products. A method is proposed for reducing switching activity, and hence power dissipation, in distributed arithmetic systems used for proce... View full abstract»

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  • Design and implementation of a nonlinear acoustic echo canceller

    Publication Year: 1998, Page(s):396 - 405
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (674 KB)

    An acoustic echo canceller based on neural networks and a fast affine projection (FAP) algorithm is introduced. This structure allows a large set of trade-offs between convergence rate, residual error, tracking capacity, and arithmetic complexity. Hence, the proposed structure has the potential for solving other difficult nonlinear adaptive signal processing tasks such as system identification whe... View full abstract»

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  • Differential Kalman filtering for tracking Rayleigh fading channels

    Publication Year: 1998, Page(s):376 - 385
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    The performance of the estimator used in the tracking of a fading channel plays an essential role in many wireless receivers. The conventional Kalman filter is an optimum estimator; however, it is computationally demanding and complex for real-time implementation. A new approach is proposed for the implementation of the Kalman filter based on differential channel states. This leads to a robust dif... View full abstract»

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  • Self-regulated GPS navigation processor

    Publication Year: 1998, Page(s):327 - 336
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (565 KB)

    We implement a navigation processor for the stand-alone global positioning system (GPS). We develop a behavior observer to monitor user dynamics and to aid a Kalman filter performing continuous position and speed estimates. The behavior observer consists of a fast observer and a signal detector. The fast observer tracks user maneuvers. The signal detector compares outputs of the fast observer and ... View full abstract»

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  • Using DG2VHDL to synthesize an FPGA implementation of the 1-D discrete wavelet transform

    Publication Year: 1998, Page(s):489 - 498
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (686 KB)

    We introduce DG2VHDL, a design tool which bridges the gap between an abstract graphical description of a DSP algorithm and its concrete hardware description language (HDL) representation. DG2VHDL automatically translates a dependence graph (DG) into a synthesizable, behavioral VHDL entity that can be input to industrial-strength behavioral compilers for producing silicon implementations of the alg... View full abstract»

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  • A system-on-chip design of a low-power smart vision system

    Publication Year: 1998, Page(s):63 - 72
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (665 KB)

    A low-power smart imager design is proposed for real-time machine vision applications. It takes advantages of recent advances in integrated sensing/processing designs, electronic neural networks, and sub-micron VLSI technology. The smart vision system integrates an active pixel camera, with a programmable neural computer and an advanced microcomputer. A system-on-a-chip implementation of this smar... View full abstract»

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  • Pentium-MMX-based implementation of a digital copier

    Publication Year: 1998, Page(s):142 - 151
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (625 KB)

    We develop real-time image processing programs for a digital copier using a general-purpose microprocessor. To exploit the inherent data parallelism in many image processing algorithms, we use Intel's Pentium processor with multimedia extension (MMX). Each step of the digital copier process including the X-Zoom and the error diffusion halftoning is aggressively optimized for the Pentium MMX proces... View full abstract»

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  • Loop scheduling algorithm for timing and memory operation minimization with register constraint

    Publication Year: 1998, Page(s):579 - 588
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    We present a novel scheduling framework, called memory operation minimization rotation scheduling (MORS), for scheduling multi-dimensional applications subject to register constraints and other resource constraints. Under such constraints, MORS strives to shorten the schedule length while minimally inserting the load and store operations in the schedule to reduce the register requirement pressure.... View full abstract»

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