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IC Design & Technology (ICICDT), 2011 IEEE International Conference on

Date 2-4 May 2011

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Displaying Results 1 - 25 of 64
  • Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1596 KB) |  | HTML iconHTML  

    New on-chip 4-bit transient-to-digital converter for electrical fast transient (EFT) protection design has been proposed. The converter is designed to detect EFT-induced transient disturbances and transfer different EFT voltages into digital codes under EFT tests. The experimental results in silicon chip have confirmed the successful digital output codes. View full abstract»

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  • ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2107 KB) |  | HTML iconHTML  

    Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM. View full abstract»

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  • Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1153 KB) |  | HTML iconHTML  

    A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25°C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition. View full abstract»

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  • Low power UTBOX and back plane (BP) FDSOI technology for 32nm node and below

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1367 KB) |  | HTML iconHTML  

    This paper highlights the interest of FD-SOI with high-k and metal gate as a possible candidate for low power multimedia technology. The possibility of multi-VT by combining UTBOX with back plane, back biasing, variable TiN thickness and Al2O3 in the gate stack is demonstrated. The viability of these approaches is corroborated via mobility and reliability measurements. Dual gate oxide co-integrated devices are reported. The effectiveness of back biasing for short devices is demonstrated through ring oscillators and 0.299 μm2 SRAM bitcells performance reflecting that the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances are fully compatible with FDSOI. Finally, thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IP's required in a SOC could be demonstrated for LP applications. View full abstract»

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  • Electrical characteristic fluctuation of 16 nm MOSFETs induced by random dopants and interface traps

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (971 KB) |  | HTML iconHTML  

    In this paper, we estimate the influences of random dopants (RDs) and interface traps (ITs) using experimentally calibrated 3D device simulation on electrical characteristics of high-κ / metal gate CMOS devices. Statistically random devices with 2D ITs between the interface of silicon and HfO2 film as well as 3D RDs inside the device channel are simulated. Fluctuations of threshold voltage and on-/off-state current for devices with different effective oxide thickness of insulator film are analyzed and discussed. The engineering findings significantly indicate that RDs and ITs govern characteristics, respectively, are statistically correlate to each other and RDs dominate device's variability, compared with the influence of ITs; however, the influence degree varies with IT's number, density and position. The effect of RDs and ITs on device characteristic should be considered together properly. Notably, the position of ITs and RDs results in very different fluctuation in spite of the same number of ITs and RDs. View full abstract»

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  • Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1129 KB) |  | HTML iconHTML  

    Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut™ technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted. View full abstract»

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  • Variability analysis of UTB SOI subthreshold SRAM considering Line-Edge Roughness, Work Function Variation and temperature sensitivity

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB) |  | HTML iconHTML  

    This paper analyzes stability and variability of Ultra-Thin-Body (UTB) SOI subthreshold SRAMs considering Line-Edge Roughness (LER), Work Function Variation (WFV) and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (μRSNM/σRSNM >; 6 at Vdd = 0.3~0.4V). Higher temperature increases the Vread, 0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs show less temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40nm and 25nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-edge work functions, the Lg = 25nm UTB SOI subthreshold SRAMs show 31.9% reduction in σ RSNM and 55% improvement in μRSNM/σRSNM compared with that using single mid-gap work function. View full abstract»

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  • 3D integrable nanowire FET sensor with intrinsic sensitivity boost

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1253 KB) |  | HTML iconHTML  

    In this paper, we review a recently developed transformative nanowire FET sensor concept and 3D-compatible fabrication technology. Compared to the generic nanowire FET sensors, an intrinsic boost in detection sensitivity is accomplished through the seamless integration of a sensing nanowire with an amplifying nanowire FET. Exclusively enabled by top-down nanofabrication technology, the back-end-of-line compatible sub-450 °C manufacturing processes have been developed. Sensing experimental data have also revealed around 1 order of magnitude sensitivity improvement in solution pH detection. Finally, an ultra-low thermal budget nanowire formation technology has been preliminarily developed for future 3D integration with CMOS. View full abstract»

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  • On the magnitude of Random telegraph noise in ultra-scaled MOSFETs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB) |  | HTML iconHTML  

    Random telegraph noise (RTN) has been shown to be a more severe scaling issue than the Random Dopant Effect (RDE). However this observation relies heavily on studies which focus only on threshold voltage (VTH) fluctuations. VTH measurements make separation of these two scaling issues (RTN and RDE) difficult. Since future scaled devices may use channels with no or low doping, it is important to examine the impact of RTN without the influence of RDE. In this work, we experimentally verify the “hole in the inversion layer” model of RTN and then use it to examine the magnitude of RTN in ultra-scaled devices without the influence of RDE. This analysis strongly suggests that RTN is a serious issue even in the absence of RDE. View full abstract»

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  • Timing error prevention using elastic clocking

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (685 KB) |  | HTML iconHTML  

    “Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking. Time borrowing allows a pipeline to compensate the timing slack by borrowing time from the next pipeline stage and clock stretching pays back the borrowed time to the next pipeline stage. Thus, a system employing such dynamic timing control technique can prevent errors with a small performance penalty and eventually operate without safety margin. The net effect is better power-performance trade-off under voltage scaling i.e. lower power consumption for a target frequency or higher operating frequency for a target power. The proposed technique was validated using a prototype test-chip designed in 180-nm CMOS technology. View full abstract»

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  • Time and workload dependent device variability in circuit simulations

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1138 KB) |  | HTML iconHTML  

    Simulations of an inverter and a 32-bit SRAM bit slice are performed based on an atomistic approach. The circuits' devices are populated with individual defects, which have realistic carrier-capture and emission behaviour. The wide distribution of defect time scales, accounts for both fast (Random Telegraph Noise - RTN) and near-permanent (Bias Temperature Instability - BTI) defects. The atomistic property of the model allows the detection of workload dependency in the delay of both circuits. View full abstract»

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  • An on-chip waveform capturer for diagnosing off-chip power delivery

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (958 KB) |  | HTML iconHTML  

    In-place diagnosis of off-chip power delivery resonance is demonstrated with on-chip waveform capturer and power delivery network (PDN) exciter that were prototyped in a 65 nm CMOS technology. Oscillatory waveforms are captured after the excitation of PDN, from which an LCR lumped equivalent circuit of PDN seen by on-chip circuits is algorithmically derived. The consistency of component values is confirmed among the demonstrated in-place diagnosis and full-wave analysis. View full abstract»

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  • Interconnect test for core-based designs with known circuit characteristics and test patterns

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (642 KB) |  | HTML iconHTML  

    System-level interconnect structures become much more complicated and dominate overall performance in multi-core systems. In order to facilitate interconnect test in board-level and system-on-chip (SoC) designs, IEEE standards 1149.1 and 1500 are developed. Dedicated design-for-testability (DFT) architectures for interconnect consisting of through-silicon via (TSV) in future 3-D stacked ICs have also been investigated. Whenever DFTs in such designs are not available due to limits of design constraints or overall cost consideration, testing those inaccessible interconnects becomes a difficult problem and it is rarely discussed in the literature. In this paper, we propose an interconnect test scheme that exploits circuit characteristics, inherent test resources in design, and test patterns of embedded cores to test interconnect. Since chips are often tested before interconnect, our scheme utilizes those good chips to propagate test patterns and observe responses of interconnect. View full abstract»

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  • Architectural-level error-tolerant techniques for low supply voltage cache operation

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    Supply voltage (VCC) scaling is the most effective technique for reducing the energy consumption of microprocessors. Since VCC scaling increases the impact of parameter variations on circuit performance and functionality, circuits eventually fall out of specification, thus limiting the minimum operating supply voltage (VCCMIN) for the microprocessor. The last-level cache (LLC) often determines VCCMIN. To maximize cache capacity, the LLC memory cell consists of near minimum-sized transistors, which are highly sensitive to process variations. For a tradition LLC, a small fraction of memory cells with large variations limit the VCCMIN for the entire microprocessor. In this paper, error-tolerant techniques dynamically reconfigure the cache to either disable or correct these failing memory cells to enable a lower VCCMIN at the cost of lower cache capacity, thus enhancing the microprocessor energy efficiency. At the high-VCC operating mode, the cache operates at full capacity to satisfy the high-performance target. At the low-VCC operating mode, energy consumption is the primary concern, and the cache is dynamically reconfigured with lower capacity to mitigate the impact of the failing memory cells on reliability. Since the clock frequency significantly reduces for the low-VCC mode as compared to the high-VCC mode, the reduction in cache capacity has a smaller effect on performance. In comparison to a traditional LLC design, simulation results indicate that the error-tolerant cache techniques decrease VCCMIN by 13-28%, corresponding to a 20-42% reduction in energy per instruction. Adding these techniques only incurs a 5-10% performance penalty at the low-VCC operating mode in comparison with a hypothetical idea cache. View full abstract»

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  • Special considerations for 3DIC circuit design and modeling

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (746 KB) |  | HTML iconHTML  

    In this paper, the new elements in 3DIC are examined for enabling optimal 3D products: including 3D interconnect which maybe the limiting factor to achievable speed; 3D chip design strategy (partition and implementation) to achive optimal performance; wireless testing to address the challenges in testing a partial system / chip before stacking and with limited observation points after stacking. View full abstract»

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  • A single TSV-rail 3D quasi delay insensitive asynchronous signaling

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB) |  | HTML iconHTML  

    Asynchronous communications are foreseen as mandatory for implementing 3D multiple tiers circuits. The drawback of asynchronous rails compared to synchronous ones is the higher number of interconnects. This number needs to be decreased when horizontal interconnects are replaced by Through Silicon Vias (TSV) because of their big silicon footprint. A circuit using only one TSV for asynchronous, quasi delay insensitive 3D signal propagation is proposed. This achieves to save two TSVs out of three, while offering 1Gbits/s capability. View full abstract»

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  • Smart stackingTM technology: An industrial solution for 3D layer stacking

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (878 KB) |  | HTML iconHTML  

    Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semiconductor applications such as Back Side Illumination (BSI) CMOS Image Sensors (CIS) as well as 3D integration approaches. View full abstract»

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  • TSV number minimization using alternative paths

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (655 KB) |  | HTML iconHTML  

    In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle TSVs at each control step. If we use idle functional units and idle TSVs to form an alternative path to replace direct TSVs for data transfer, the number of TSVs can be reduced. Based on that observation, we present an ILP (integer linear programming) approach to formally draw up our problem. Given a high-level synthesis result and a clock period constraint, we perform post-processing to fully utilize alternative paths for TSV number minimization. Compared with previous work that minimizes the TSV number without considering alternative paths, experimental results show that our approach can further reduce 16.92% TSV number without affecting the circuit performances. View full abstract»

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  • Through Silicon Via technology using tungsten metallization

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1074 KB) |  | HTML iconHTML  

    Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different approaches can be considered. The TSV's can be done before the FEOL (pre-process approach) or in-between the FEOL and the BEOL (mid process approach). Each solution has advantages and drawbacks depending on the final application in particular. In a first part of this paper the tungsten mid-process TSV technology will be presented and briefly compared to the copper mid-process approaches. Then, the process of the tungsten TSV fabrication will be detailed and morphological characterizations will be presented. We will focus on two specific parts of the process which have been specifically optimized for the tungsten TSV technology: the low temperature insulation oxide and the tungsten deposition-etch back sequence to fill the vias. The results of those optimizations will be presented and discussed. Last, we will introduce the electrical test vehicle used in this work and present the main results regarding via resistances. Some specific recommendations will by proposed in term of design and integration rules in relation with the process constraints. View full abstract»

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  • Statistical delay calculation with Multiple Input Simultaneous Switching

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (716 KB) |  | HTML iconHTML  

    The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical analysis method to capture statistical gate delay variations, able to accurately handle MISS. Experiment results obtained with a 45 nm technology show that our approach accurately obtains not only mean and standard deviation, but also the third moment, skewness. View full abstract»

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  • Balanced Truncation of a stable non-minimal deep-submicron CMOS interconnect

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (661 KB) |  | HTML iconHTML  

    As the widening of process variability in submicron CMOS technology calls for accurate timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. In this context, model order reduction techniques have been used extensively to reduce the complexity of extracted interconnect circuits and to expedite fast and accurate circuit simulation. In the interconnect modeling, solving large-scale Lyapunov equations arises as a necessity in model order reduction techniques based on Balanced Truncation. In this paper, within this framework, dominant eigensubspaces of the product of the system Gramians are approximated directly. We construct orthogonal basis sets for the dominant subspaces of controllability and observability Gramians and perform eigenvalue decomposition to reduce the cost of singular value decomposition. As the experimental results indicate, the proposed approach can significantly reduce the complexity of interconnect, while retaining high accuracy in comparison to the original model. View full abstract»

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  • Enabling TLM-2.0 interface on QEMU and SystemC-based virtual platform

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    This paper presents a QEMU and SystemC-based virtual platform that is capable of hardware modeling using TLM-2.0 interface. The proposed virtual platform is not only capable of running an operating system, but it is also capable of using such an interface to connect hardware models, such as the instruction set simulator to a bus model. We verify the functionality of such a platform by using it to boot up a full-fledged Linux while at the same time estimating its performance at the instruction-accurate level. Furthermore, TLM-2.0 interface makes our framework more compatible with other models using TLM-2.0 and more suitable for modeling at the early stage of ESL design flow. View full abstract»

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  • A fast custom network topology generation with floorplanning for NoC-based systems

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (698 KB) |  | HTML iconHTML  

    This paper proposes a fast full-chip synthesis methodology which can be built a custom Network-on-Chip (NoC) topology for NoC-based systems. The processors and their communications are synthesized simultaneously in the system-level floorplanning process. The proposed method leads to accurate area estimation, which makes an algorithm much more efficient than previous approaches. Moreover, the wirelength-aware floorplanning is carried out to optimize circuit size as well as wire length. As a result, experimental results show that the proposed approach produces custom NoCs with better performance than previous methods while the computation time is significantly shorter. This method is also more scalable, which makes it ideal for complicated NoC-based systems. View full abstract»

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  • Evolution of embedded flash memory technology for MCU

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (778 KB) |  | HTML iconHTML  

    Embedded flash memory technology has undergone tremendous growth of demands with various performance requirements driven by expanded applications of MCU (Micro Controller Unit) products. High temperature operations with highest reliability for auto-motive applications, very low power embedded EEPROM functions for smart-cards, and ultra low-voltage operations for medical applications are driving factors in developing embedded flash technologies. Together with evolving memory cell technology, resolving performance/power trade-offs by developing dedicated design platforms with optimized eFlash technology, memory interface & bus designs, and the whole chip design methodologies, has realized advanced MCU products line-ups by split-gate MONOS flash technology with a wide range of applied products including auto-motive and security applications. View full abstract»

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  • Impacts of intrinsic device variations on the stability of FinFET subthreshold SRAMs

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1979 KB) |  | HTML iconHTML  

    In this work, we investigate the impacts of intrinsic device variations on FinFET subthreshold SRAMs, including the conventional tied-gate 6T SRAM, tied-gate 10T Schmitt Trigger based SRAMs, and recently proposed independent-gate controlled 8T Schmitt Trigger based SRAMs. The impacts of intrinsic random device variations, including Fin Line-Edge Roughness (LER) and Work Function Variation (WFV), on the device threshold voltage Vth, Subthreshold Swing (S.S.) and stability of FinFET SRAMs operating in subthreshold region are assessed using 3D atomistic mixed-mode Monte-Carlo simulations. The results indicate that Fin LER is the dominant factor limiting the stability of FinFET subthreshold SRAMs, since Fin LER degrades both Vth fluctuation and S.S., while WFV mainly affects only Vth fluctuation. The independent-gate controlled Schmitt Trigger SRAMs are shown to offer adequate stability for the intended subthreshold applications even considering intrinsic device variations. View full abstract»

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