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Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on

Date 1-3 May 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): C1
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  • [Title page i]

    Publication Year: 2011, Page(s): i
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  • [Title page iii]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - ix
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  • Message from the General and Program Chairs

    Publication Year: 2011, Page(s):x - xi
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  • Organizing Committee

    Publication Year: 2011, Page(s): xii
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  • Program Committee

    Publication Year: 2011, Page(s):xiii - xiv
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  • Additional Reviewers

    Publication Year: 2011, Page(s): xv
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  • Preconference Workshop Summary

    Publication Year: 2011, Page(s): xvi
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  • Panel Session Summary

    Publication Year: 2011, Page(s): xvii
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  • Sponsors

    Publication Year: 2011, Page(s): xviii
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  • A Sparse Matrix Personality for the Convey HC-1

    Publication Year: 2011, Page(s):1 - 8
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (625 KB) | HTML iconHTML

    In this paper we describe a double precision floating point sparse matrix-vector multiplier (SpMV) and its performance as implemented on a Convey HC-1 reconfigurable computer. The primary contributions of this work are a novel streaming reduction architecture for floating point accumulation, a novel on-chip cache optimized for streaming compressed sparse row (CSR) matrices, and end-to-end integrat... View full abstract»

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  • Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification

    Publication Year: 2011, Page(s):9 - 16
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (365 KB) | HTML iconHTML

    Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the functional verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing... View full abstract»

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  • Mixed Precision Processing in Reconfigurable Systems

    Publication Year: 2011, Page(s):17 - 24
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (349 KB) | HTML iconHTML

    Customisable data formats provide an opportunity for exploring trade-offs in accuracy and performance of reconfigurable systems. This paper introduces a novel methodology for mixed-precision comparison, which improves comparison performance by using reduced-precision data paths while maintaining accuracy by using high-precision data paths. Our methodology adopts reduced-precision data-paths for pr... View full abstract»

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  • Dynamic Communication in a Coarse Grained Reconfigurable Array

    Publication Year: 2011, Page(s):25 - 28
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    Coarse Grained Reconfigurable Arrays (CGRAs) are typically very efficient for a single task. However all functional units are required to perform in lock step, wasting resources and making complex programming flows difficult. Massively Parallel Processor Arrays (MPPAs) excel at executing unrelated tasks simultaneously, but limit the amount of resources dedicated to a single task. We propose an arc... View full abstract»

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  • Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors

    Publication Year: 2011, Page(s):29 - 32
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB) | HTML iconHTML

    State-of-the-art multi-core reconfigurable processors do not exploit the full potential of simultaneous multi-tasking with run-time adaptive reconfigurable fabric allocation. We propose a novel run-time system for simultaneous multi-tasking in a multi-core reconfigurable processor that adaptively allocates the mixed-grained reconfigurable fabric resource at run time among different tasks consideri... View full abstract»

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  • An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs

    Publication Year: 2011, Page(s):33 - 36
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (443 KB) | HTML iconHTML

    We present a Floating Point Vector Coprocessor that works with the Xilinx embedded processors. The FPVC is completely autonomous from the embedded processor, exploiting parallelism and exhibiting greater speedup than alternative vector processors. The FPVC supports scalar computation so that loops can be executed independently of the main embedded processor. Floating point addition, multiplication... View full abstract»

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  • Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA Board

    Publication Year: 2011, Page(s):37 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (278 KB) | HTML iconHTML

    This paper proposes techniques for face detection and gives the implementation details for an FPGA development board. We analyze and discuss the relation between the system computation cost and selection of the image scaling factor. We give a new method to select the stop threshold for the image reduction process, which reduces the total computation by half. We also provide a color image output mo... View full abstract»

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  • An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

    Publication Year: 2011, Page(s):41 - 48
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1453 KB) | HTML iconHTML

    Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns bett... View full abstract»

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  • Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUs

    Publication Year: 2011, Page(s):49 - 56
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1046 KB) | HTML iconHTML

    Fourier Domain Optical Coherence Tomography (FD-OCT) is an emerging biomedical imaging technology featuring ultra-high resolution and fast imaging speed. Due to the complexity of the FD-OCT algorithm, real time FD-OCT imaging demands high performance computing platforms. However, the scaling of real-time FD-OCT processing for increasing data acquisition rates and 3-dimensional (3D) imaging is quic... View full abstract»

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  • Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU

    Publication Year: 2011, Page(s):57 - 64
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (454 KB) | HTML iconHTML

    The Lightfield descriptor method for 3D computer graphics offers the highest quality object retrieval from a database at the expense of higher storage and computational cost vs. other methods. This paper presents two special purpose architectures, based on FPGAs and GPUs, for the depth buffer extraction algorithm which is used by the Light field Descriptor method. The two architectures were fully ... View full abstract»

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  • Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors

    Publication Year: 2011, Page(s):65 - 68
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    Accelerators, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), are special purpose processors designed to speed up compute-intensive sections of applications. FPGAs are highly customizable, while GPUs provide massive parallel execution resources and high memory bandwidth. In this paper, we compare the performance of these architectures, presenting a performance ... View full abstract»

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  • FPGA Communication Framework

    Publication Year: 2011, Page(s):69 - 72
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a host-software library/API. It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard internet protocols. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports al... View full abstract»

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  • Efficient Calculation of Pairwise Nonbonded Forces

    Publication Year: 2011, Page(s):73 - 76
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (626 KB) | HTML iconHTML

    A major bottleneck in molecular dynamics (MD) simulations is the calculation of the pair wise nonbonded interactions. Previous work on FPGAs has shown that these calculations can be implemented with a number of force computation pipelines operating in parallel (4 and 8 for the Stratix-III and Stratix-V, respectively). Optimization has received some attention previously in CPU, GPU, FPGA, and ASIC ... View full abstract»

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