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Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Date 6-9 Dec. 2010

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Displaying Results 1 - 25 of 315
  • [Title page]

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  • Welcome message

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    It is my great pleasure to welcome you to Kuala Lumpur on behalf of the IEEE Circuits and System Society Malaysia Chapter to attend the 10th biennial the 2010 IEEE Asia Pacific Circuits and Systems Conference (APCCAS2010). In this conference, we offer all delegates an exciting technical program that showcases the recent development in the field of circuits and systems. In addition, we hope all delegates find time while exchanging ideas to have fun, fun for enjoying the country which is also known as truly Asia. View full abstract»

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  • Technical program co-chairs' message

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    On behalf of the technical program committee, we are pleased and honored to invite and welcome you to Malaysia and to the 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010). In APCCAS 2010, the technical program shows the novel and advanced development in the field of circuits and systems. We also hope all attendees have fun in enjoying the history and cultures of Malaysia. View full abstract»

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  • Conference organization

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  • Table of contents

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  • Versatile high input impedance voltage-mode three-inputs universal biquadratic filter

    Page(s): 1 - 4
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    This paper presents a new high input impedance voltage-mode universal biquadratic filter with three inputs and six outputs using three plus-type differential difference current conveyors (DDCCs), two grounded capacitors, and three resistors. The proposed circuit can realize all the standard filter functions (low-pass, high-pass, band-pass, notch, and all-pass). Moreover, the circuit enjoys (i) the employment of two grounded capacitors, (ii) high input impedance and (iii) low active and passive sensitivity performance. HSPICE simulation results confirm the theoretical analysis. View full abstract»

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  • A tunable transconductor with high linearity

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    In this paper a high frequency low voltage low power tunable highly linear transconductor is presented. Shift level biasing is used at the inputs of both the amplifiers of a cross coupled differential pair for tuning. Bias currents of cross coupled differential amplifiers are adjusted to cancel third harmonic distortion. The proposed circuit is simulated in Cadence VIRTUOSO environment with UMC 0.18 μm CMOS process technology. Simulation results show that for the biasing current of 206 μA (Gm of 222 μS), the circuit exhibits less than -51 dB total third harmonic distortion (HD3) at 1 Vp-p @ 50 MHz. View full abstract»

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  • An unconditionally stable Voltage Regulator

    Page(s): 9 - 12
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    This paper describes a CMOS implementation of a Linear Voltage Regulator (LVR) used to power implanted systems. The topology is based on a classical structure of a Low Dropout Regulator (LDO) and receives his activation energy from a RF link characterizing a passive RFID tag. The LVR was designed to achieve important features like low power consumption, and a small silicon area without the need for any external discrete components. The project was implemented in a 0.35 μm CMOS process and a prototype was tested to validate the overall performance. The LVR output is regulated at 1V and supplies a maximum load current of 0.5 mA @ 37°C. The load regulation is 13 mV/mA and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW. View full abstract»

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  • A new offset cancelled latch comparator for high-speed, low-power ADCs

    Page(s): 13 - 16
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    A new high speed, low power and high resolution comparator architecture is presented. Offset voltage cancellation on latch stage and eliminating the preamplifier stages before regeneration latch in conventional architectures is the key idea proposed in this paper. Equivalent input referred offset voltage is dramatically reduced by controlled negative feedback loop and negative resistance of regeneration latch. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 0.2 mV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator operates in 500 MHz clock frequency while dissipates 600 μW from a 1.8V supply. View full abstract»

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  • Low power chopper amplifier without LPF

    Page(s): 17 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (907 KB) |  | HTML iconHTML  

    Chopping technique is an efficient approach to decrease the 1/f noise and low-frequency offset of CMOS amplifiers, but conventional chopper amplifier consumes large power because it required a wide-band amplifier exceed a chopping frequency and a post low pass filter (LPF) for eliminating modulation noise. In this paper, an improved chopper amplifier for reducing power consumption is presented which is composed of a two-stage amplifier. The high output impedance of the first stage folded cascode amplifier and the equivalent Miller capacitance constitute together a LPF to filter out the modulation noise, so the chopper amplifier need not the post LPF, which can reduce the power consumption. The circuit of the presented chopper amplifier is designed in TSMC 0.18μm CMOS technology. The chopper amplifier consumes 20 μA current and 36 μW power at 1.8V supply. The equivalent input noise voltage is 73nV/√(Hz) @1Hz and the input noise voltage integrated from 0.1Hz to 150Hz is 0.68μV rms. View full abstract»

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  • FPGA-based architectures of finite radon transform for medical image de-noising

    Page(s): 20 - 23
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    This paper presents the design and implementation of finite Radon transform (FRAT) on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. FPGA-based architectures with three design strategies have been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)-based approach. Various medical images modalities have been deployed for both software simulation and hardware implementation. An analysis on the image de-noising using the FRAT is addressed and demonstrates a promising capability for medical image de-noising. Moreover, the impact of different block sizes on reconstructed images has been analysed. Furthermore, performance analysis in terms of area, maximum frequency and throughput is presented and reveals a significant achievement. View full abstract»

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  • Design and development of a low cost EMG signal acquisition system using surface EMG electrode

    Page(s): 24 - 27
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    Electromyogram or EMG signal is a very small signal; it requires a system to enhance for display purpose or for further analysis process. This paper presents the development of low cost physiotherapy EMG signal acquisition system with two channel input. In the acquisition system, both input signals are amplified with a differential amplifier and undergo signal pre-processing to obtain the linear envelope of EMG signal. Obtained EMG signal is then digitalized and sent to the computer to be plotted. View full abstract»

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  • A low-power remotely-programmable MCU for implantable medical devices

    Page(s): 28 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (967 KB) |  | HTML iconHTML  

    This paper presents a low-power MCU with remotely-programmable feature which is specifically optimized for implantable medical devices (IMDs). In medical applications the most critical requirements are low-power, energy-efficient, flexible, etc., which are provided by utilizing the techniques such as clock gating, power gating, instruction set improvement, DMA optimizations for data paths. The MCU has been verified correctly and fabricated with a scale of 79.1K equivalent gates, in standard 0.18μm CMOS technology. View full abstract»

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  • A wireless energy link for endoscopy with end-fire helix emitter and Load-Adaptive power converter

    Page(s): 32 - 35
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    This paper proposes a new Wireless-Powered Micro-Ball Endoscopy system, in which wireless power is emitted from an emitter array embedded in a floor and resonantly relayed by a passive wireless power jacket on patients. Comparing to other wireless powering endoscopy systems, both the patients' freedom of movement and the power efficiency are improved. To enhance the power efficiency, an End-Fire Helix Emitter is proposed, which is a fundamentally novel structure used for generating near field alternative magnetic field with high efficiency. This paper also proposes a Load-Adaptive power converter circuit to keep optimal power efficiency by matching the varied load impedance. A prototyping design is fabricated. At the frequency of 24.05MHz, the power efficiency of transmission from floor to wireless jacket is 44.6%, and the overall energy efficiency from floor to Endoscopic Micro-Ball is 2.5% at best. View full abstract»

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  • A 77 nW bioamplifier with a tunable bandwidth for neural recording systems

    Page(s): 36 - 39
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    In this paper a low-power low-noise amplifier for neural recording and biomedical applications is presented. The frequency band of the amplifier is tunable. It has a gain of 28.3 dB. The low and the high cut-off frequency can be adjusted from 24 mHz to 30.6 Hz and 4.5 kHz to 7.47 kHz, respectively. The circuit is designed in 0.18μm CMOS process, and it consumes only 77.8 nW at 1.8V supply voltage. The simulation results show a 14.3μV input-referred noise corresponding to 1.32 efficiency factor (NEF). It is a great improvement compared with recent presented works in terms on power consumption and NEF which is vital in neural recording applications. View full abstract»

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  • Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overhead

    Page(s): 40 - 43
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    For SoCs (Sea of Cores!) which contains a large amount of IP cores with pre computed test data, the code based test data compression scheme is more suitable as it does not require any knowledge of internal nodes of IP. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this paper, the five different approaches for don't care bit filling based on nature of runs are proposed. These methods are used here to predict the maximum compression based on entropy relevant to different run length based data compression code. These methods are also analyzed for test power and area overhead corresponding to run length based codes. The results are shown with various ISCAS circuits. View full abstract»

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  • ADC linearity test signal generation algorithm

    Page(s): 44 - 47
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    This paper describes an algorithm for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test low-sampling-rate, high-resolution ADCs. We here propose to generate a test signal consisting of multiple sine waves, to precisely test the linearity for specific important codes (such as around the center of the output codes), using an arbitrary waveform generator (AWG) and an analog filter. We have performed MATLAB simulation to validate our algorithm, and the results show that in some cases the testing time can be reduced to half that for conventional sine wave histogram testing. View full abstract»

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  • A design platform for analog device size sensitivity analysis and visualization

    Page(s): 48 - 51
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    A symbolic calculation method for the sensitivity of frequency response to semiconductor device sizes is addressed for application in analog integrated circuit design. The transistor-size-based ac-sensitivity can be used for sizing devices and understanding the circuit behavior. Examples are provided to demonstrate that a design platform supported by symbolic ac-sensitivity and visualization can be a helpful tool for computer-aided design of analog integrated circuit. View full abstract»

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  • Jitter generation and capture using phase-domain sigma-delta encoding

    Page(s): 52 - 55
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    This article presents techniques and circuits for jitter generation and measurement. The proposed implementations use periodic bit-streams and high-order PLLs to generate the desired phase signal. Here, an arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the phase-domain through a digital-to-time converter (DTC) process realized in software. The resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-domain filter. The parameters of the sigma-delta modulator along with those of the high-order PLL can be traded for one another to achieve maximum performance. The method to generate the sigma-delta encoded phase signal and to design the high-order PLL is presented. A high quality Gaussian jitter signal has been experimentally generated. Also, a setup using DC encoded phase shifts serving as an under-sampling clock to measure jitter with a 50 GHz effective sampling rate has also been experimentally proven. The conciseness and digital nature of the jitter generation scheme together with the jitter measurement architecture makes them easily amenable to a design-for-test framework. View full abstract»

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  • Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits

    Page(s): 56 - 59
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    This paper presents a built-in self-test/repair (BISTR) scheme for through-silicon via (TSV) based three-dimension integrated circuits (3D ICs). The proposed BIST structure focuses on the testing of a specific defective TSV by using a critical value of threshold. Then, the test results from BIST will be delivered to the BISR structure for repairing the defective TSV. Additionally, a parallel processing approach is presented of the proposed BISTR scheme to speed up the operations of test and repair. Experimental results demonstrate that the proposed BISTR scheme can achieve the good performance in repair rate and yield with little area overhead penalty. View full abstract»

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  • A 4.8-Gb/s mixed-mode CMOS QPSK demodulator for 60-GHz wireless personal area networks

    Page(s): 60 - 63
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    A mixed-mode QPSK demodulator for 60-GHz wireless personal area network application is demonstrated. The prototype chip realized by 60-nm CMOS process can demodulate up to 4.8-Gb/s QPSK signals at 4.8-GHz carrier frequency. At this carrier frequency, the demodulator core consumes 54 mW from 1.2-V power supply while the chip area is 150 × 150 μm2. Using the fabricated chip, transmission and demodulation of 1.7-GSymbol/s QPSK signal in 60-GHz link is demonstrated. View full abstract»

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  • Design of high linearity low flicker noise 5.2 GHz down-conversion mixer for direct conversion receiver

    Page(s): 64 - 67
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    A design of high linearity (IIP3), low flicker noise (NF), high conversion gain (CG) double-balanced Gilbert-cell mixer (DBGCM) is presented. Since the performance of a direct conversion receiver (DCR) is strongly affected by linearity and flicker noise (1/f) of a mixer in receiving side, a hybrid technique of dynamic current injection (DCI), a tuned inductor in switching pair and direct superposition method are employed to improve the flicker noise corner frequency, conversion gain and IIP3 of a DBGCM without affecting the other parameters. The mixer is designed and implemented on 0.18 μm CMOS technology and a few of the measured results were presented. The proposed mixer has a simulated conversion gain of 14dB, while the IIP3 at +13 dBm, single side band (SSB) noise figure is 8.4dB (@ 100 kHz). View full abstract»

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  • A low flicker noise, highly linear, direct conversion receiver for 5GHz wireless LAN

    Page(s): 68 - 71
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    In this paper a low flicker-noise highly linear 5 GHz direct conversion receiver (DCR) has been proposed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor for output flicker noise (1/f) reduction. Derivative superposition (DS) technique has been used in the mixer circuit to enhance the linearity. The DCR has been designed and fabricated using TSMC 0.18μm 1P6M CMOS technology. The proposed DCR achieves 7.2dB SSB-NF, 25dB conversion gain, 4dBm IIP3, and flicker noise corner frequency of 100KHz with 72mW power consumption from 1.8V supply voltage. View full abstract»

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  • An electrically small meander line antenna for wireless applications

    Page(s): 72 - 75
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    The meander line antenna (MLA) is conventionally an electrically small antenna. Electrically small antennas pose several performance related issues such as narrow bandwidth, high VSWR, low gain and high cross polarization levels. In this paper a modified two element MLA is proposed. The modified MLA possesses novelty in terms of its geometrical shape, which is achieved with the unification of the two MLA elements. This altered geometry helped in better input impedance matching with the MLA elements and consequently achieving the dual band operation. The proposed antenna is designed to cater the ISM (Industrial, Scientific, Medical) bands of 2.45 and 5 GHz. The antenna performance parameters are optimized to achieve reasonably wide impedance bandwidth, low VSWR, high gain and an omnidirectional radiation pattern. Moreover, the current distribution and the effect of the ground plane size on the altered MLA are discussed in this paper. View full abstract»

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  • A 47-dB linear CMOS variable gain amplifier using current squaring technique

    Page(s): 76 - 79
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    In this paper, a CMOS linear-in-dB variable gain amplifier (VGA) is presented. The VGA consists of exponential control block which includes a current squaring circuit, amplifier block and common mode feedback block. Based on the current squaring block which doubles the gain range, a 47dB (-20dB to 27dB) continuous gain range is achieved with a single-stage structure. Simulation results show that the VGA core consumes 3mA of current from a 1.2V supply and has a 3-dB bandwidth greater than 200MHz. The IIP3 and the input referred noise density are within the ranges of 3 to -17dBm and 5 to 68 nV/sqrt(Hz) respectively. View full abstract»

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