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Microelectronics and Electron Devices (WMED), 2011 IEEE Workshop on

Date 22-22 April 2011

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  • [Title page]

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  • [Copyright notice]

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  • Table of contents

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  • Welcome to the 2011 IEEE WMED

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  • IEEE WMED 2011 management Committee

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  • IEEE WMED 2011 technical program

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  • Keynote talk: Atoms to go…ionic memory and data storage

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    The adoption of novel materials and device structures will be necessary to overcome the growing limitations of existing memory technologies such as DRAM and Flash in low energy computation and ultra-mobile applications. The alternative that appears to have risen above the other new technology contenders is “resistive memory”, in which information is represented by different values of electrical resistance. In one particularly promising low energy approach to this type of memory, resistance is controlled by the movement of ions coupled with electrochemical processes. These “ionic” resistance-change devices are generally divided into cation cells, based on the growth and dissolution of conductive metallic filaments in a relatively insulating solid electrolyte, and anion cells, which typically utilize the formation and removal of conducting sub-oxide regions in insulating transition metal oxides. Ionic memory is now under investigation in some of the world's top research institutes and companies and has gained sufficient momentum and acceptance to be included in the International Technology Roadmap for Semiconductors. This presentation will focus on the materials and operational characteristics of ionic memory, and will discuss, by way of examples from academia and industry, why this technology will likely make its way into data centers and hand-held devices in the not-too-distant future. View full abstract»

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  • Invited tutorial: Advanced CMOS transistor technology: Past, present and future

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    Almost half a century later, Gordon Moore's accurate observation that the number of transistors in an integrated circuit doubles every two years continues to be the guiding principle of the semiconductor industry. We have almost taken for granted the apparent corollary; as transistor count increases, each transistor becomes smaller, faster and cheaper. Today, the transistor physical gate length in production is less than 30 nanometer; further brute-force geometric scaling of conventional silicon devices limit faces many fundamental challenges - rising energy consumption, power density and worsening device to device fluctuation being some of the foremost barriers. In this tutorial, I will present the amazing journey of the logic transistor in the last ten years starting with strained channel CMOS transistors, the high-k/metal-gate silicon CMOS transistors and the multiple-gate transistor architecture. Then, I will review the recent breakthroughs in non-silicon (compound semiconductor and germanium) based quantum-well transistor research that are promising transistor architecture for the next decade. I will also describe our research efforts in a new genre of “green” transistors that work on the quantum-mechanical band to band tunneling principle called Tunnel transistors and can operate with the record low energy delay product. Finally, interaction of emerging devices with the circuit and system architecture will also be discussed. This talk will summarize the twenty-first century logic transistor innovations that have and will continue to enhance the energy efficiency and performance of information processing systems through materials, device physics and architectural innovations. View full abstract»

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  • Invited tutorial: Energy efficient multi-Gb/s I/O: Circuit and system design techniques

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    Abstract form only given. Chip-to-chip I/O data rates continue to scale aggressively to keep up with demands brought on by multi-core CPU-based computer and networking systems. Due to increasing bandwidth needs and declining system power budgets, dramatically improving I/O energy efficiency is crucial and is the major challenge currently facing the computer and networking industry. A multi-pronged approach to I/O power reduction will be presented, employing both circuit and interconnect optimization. The use of system level modeling and optimization to co-design the packaging, board interconnect, channel, transmitter, receiver, and clocking will be advocated with examples that demonstrate minimum-power I/O systems. I/O energy reduction depends on both active power minimization as well as the use of aggressive power management methods. Techniques and corresponding examples will be shown that demonstrate I/O power management including dynamic voltage and frequency scaling, low-power standby, and fast wake-up times. This session will provide insight into the challenges and opportunities associated with each low-power technique, using case studies to illustrate state-of-the-art low-power I/O systems. View full abstract»

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  • Invited talk: Promises and challenges in light-emitting diodes for lighting applications

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    Lighting technologies based on semiconductor light-emitting diodes (LEDs) offer unprecedented promises that include three major benefits: (i) Gigantic energy savings enabled by efficient conversion of electrical energy to optical energy; (ii) Substantial positive contributions to sustainability through reduced emissions of global-warming gases, acid-rain gases, and toxic substances such as mercury; and (iii) The creation of new paradigms in lighting driven by the unique controllability of solid-state lighting sources. Due to the powerful nature of these benefits, the transition from conventional lighting sources to solid-state lighting is virtually assured. This presentation will illustrate the new world of lighting including the pervasive changes to be expected in lighting, displays, communications, and biotechnology. The presentation will also address the formidable challenges that must be addressed to further advance solid-state lighting technology. These challenges offer opportunities for research and innovation. Specific challenges include light management and carrier transport. As an example, we will discuss new optical thin-film materials with a tunable refractive index. We will also discuss the hotly debated efficiency droop, that is, the decreasing LED efficiency at high currents. View full abstract»

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  • Invited talk: Label-free biosensing with silicon nanowires

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    Nanoscale electronic devices have the potential to achieve exquisite sensitivity as sensors for the direct detection of molecular interactions, thereby decreasing diagnostics costs and enabling previously impossible sensing in disparate field environments. Semiconducting nanowire-field effect transistors (NW-FETs) hold particular promise, though contemporary NW approaches are inadequate for realistic applications. We present here a number of top-down fabricated nanowire approaches that are compatible with complementary metal-oxide-semiconductor (CMOS) technology that has not only achieved unprecedented sensitivity, but simultaneously facilitates system-scale integration of nanosensors. These approaches enable a wide range of label-free biochemical and macromolecule sensing applications, such as specific protein and complementary DNA recognition assays, and specific macromolecule interactions at <;femtomolar concentrations. We will also discuss the physics of FET sensing, and device-related limits of potential detection.A critical limitation of nanowire sensors is the Debye screening issue [3] which has to date prevented their use in clinical applications and physiologically relevant solutions. We will present an approach that solves this longstanding problem, and demonstrate the detection at clinically important concentrations of biomarkers from whole blood samples [4]. View full abstract»

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  • Structural study of Ag-Ge-S solid electrolyte glass system for resistive radiation sensing

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    Solid electrolytes based on chalcogenide glasses have been one of the most promising candidates for the next generation non-volatile memories. Here we propose a new application of chalcogenide solid electrolytes for low cost, high performance microelectronic radiation sensor that reacts to γ-radiation to produce an easily measurable change in electrical resistance. The active layer material is Ag-doped GeS thin film glasses and several compositions of GeS base glasses were tested for best resistive sensing capability. Energy-dispersive X-ray spectroscopy (EDS) was used for elemental analysis and Raman scattering spectroscopy was measured to determine the structural details and radiation induced structural changes. We also present initial electrical measurement results with test devices. View full abstract»

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  • Friction based endpoint technique for barrier polish during copper CMP

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    A novel method has been introduced to provide a clear endpoint signal for copper CMP barrier polish with minimal time delay as compared to conventional endpoint. A modified power sensor is installed on a 300mm polisher to measure the torque generated by the platen motor with an improved signal to noise ratio. An Extended Kalman filter (EKF) is integrated to the software to extract the friction signals while discarding the sinusoidal components due to carrier head and platen movement, and reveal clear friction endpoint. The intensity of signal is improved by changes in process and/or slurry parameters. The technique is validated by using blanket barrier films as well as patterned wafers. View full abstract»

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  • Finite element modeling of a back grinding process for Through Silicon Vias

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    The optimization of grinding parameters for silicon wafers is necessary in order to maximize the reliability of electronic packages. This paper describes the work performed to simulate a back grinding process for Through Silicon Via (TSV) wafers using the commercial finite element code ABAQUS. The grinding of a TSV silicon wafer with a thickness of 120 μm mounted on a backing tape was simulated. The wafer was thinned to a thickness of 115.5 μm, by simulating the grinding with a diamond particle cutting through successive silicon and copper layers. The computed residual stresses induced in the wafer were compared with experimental values, and the plastic deformation in the simulated ground surface was compared with literature data and showed good correlation. The numerical model developed can be used to better understand the local grinding parameters in the TSV wafers and the effect of the of the copper vias on the wafer properties. View full abstract»

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  • VT statistics on nanoscale NAND Flash arrays

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    This paper presents a compact model allowing the investigation of the variability effects in nanoscale NAND Flash arrays. The proposed model describes the NAND string current in the readout conditions, including parasitic capacitive couplings among neighboring cells, and also the cell programming and erase operations. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of the cell threshold-voltage is obtained for state-of-the-art and next generation technology nodes. Good agreement between simulations and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on NAND technology design. View full abstract»

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  • High-performance transistor evaluation for low-cost embedded DRAM

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    High-speed and low-power logic compatible performance is in high demanded for embedded DRAM (eDRAM) and/or custom DRAM applications. However, it is a challenge to make it cost-effectively using the commercial DRAM process. In this paper, the feasibility of high-performance transistors is demonstrated using the commercial Micron Technology 95 nm DRAM process and design targeted for low-cost eDRAM. Multiple process conditions were optimized in the commercial DRAM process to simultaneously achieve the target performance and minimize DRAM retention time degradation. A dual-EPI process-thin selective EPI growth in the peripheral source/drain and thick selective EPI growth in the DRAM cell array-was experimentally developed to improve DRAM retention time. Parametrically, the dual-EPI process was successful, but further optimization is required for good yield. View full abstract»

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  • Self-calibrating continuous-time equalization with multiple degrees of freedom

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    A method for designing self-calibrating continuous-time equalizers is proposed. A pair of error terms, derived from the channel pulse response, may be used to adaptively calibrate the equalizer, resulting in a significant reduction of inter-symbol interference (ISI). Matlab simulations show the clear opening of a twenty Gigabit/second (Gb/s) data eye at the end of a six inch FR4-based signal route. View full abstract»

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  • Adjustable supply voltages and refresh cycle for process variations and temperature changing adaptation in DRAM to minimize power consumption

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    In this paper, we propose an approach to dynamically adjust supply voltages and refresh cycle in Dynamic Random Access Memory (DRAM). With this approach, we can save the chip power consumption with an awareness of process variations and temperature changing. While DRAM systems are generally designed for the worst case condition, they seldom operate under those scenarios. Thus, we can exploit the design slack when operating under more favorable conditions to save power. Simulations showed that it is possible to save power consumption by as much as 40%. View full abstract»

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  • All digital duty-cycle correction circuit design and its applications in high-performance DRAM

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    Duty-cycle distortion (DCD) becomes a pressing concern as the data rate in high-performance DRAM interfaces exceeds multi-gigahertz range. In order to preserve or even improve the clock duty cycle on-die across process, voltage, and temperature (PVT) corners, a duty-cycle correction (DCC) circuit is generally desired. This paper investigates a variety of DCC circuits based on different implementations. Two applications using DCC circuits are presented in detail: 1) a digital DCC for high-speed data capture, and 2) an all-digital DCC for production DDR3 DRAMs. Pros and cons for the different approaches are compared based on the simulated and silicon data. View full abstract»

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  • A non-volatile memory array based on nano-ionic Conductive Bridge Memristors

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    Much excitement has been generated over the potential uses of chalcogenide glasses and other materials in circuits as “memristors” or as non-volatile memories. The memristor is a fourth passive two terminal electronic device, postulated by Leon Chua in 1971 and rediscovered in 2008. Our Conductive Bridge Memristor (CBM) changes its resistance in response to current passing through it by building up or dissolving a conductive molecular bridge in an otherwise insulating chalcogenide film. This paper outlines the design and simulation of a non-volatile memory using an array of CBM devices integrated with CMOS access transistors and read/write access circuitry. We have designed and simulated a large memory array layout using CBM devices accessed by an NMOS transistor and CMOS row/column read and write drivers. The design uses a folded-cascode op-amp configured to integrate current on the column as a strategy for sensing the device resistance. Each CBM device is connected to the array through a single minimum size NMOS transistor. The design has been simulated using a SPICE model for the PMC (Programmable Metallization Cell). We demonstrate the feasibility of accessing the device for read without exceeding the write threshold, and discuss the tradeoff of speed vs. array size associated with this technique. Plans are being developed to fabricate the design on a MOSIS multi project wafer with BEOL processing for the CBM devices. View full abstract»

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  • Optimized Germanium co-implant with B2H6 PLAD for better advanced PMOS device performance

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    The following abstracts are given: Optimized Germanium Co-Implant with B2H6 PLAD for Better Advanced PMOS Device Performance; Design of low noise CMOS charge pump with adjustable output voltage and adjustable power; Measurement and Simulation of Various Geometries of LTCC Electron Hop Funnels; Efficient Design and Synthesis of Decimation Filters for Wideband Delta-Sigma ADCs; A Novel Material Solution for Non Volatile Contact Bridge Memristive Memory Fabrication; Radiation induced effects in pure and Ag doped Ge-Se films; and Design Techniques for a 70 Gbps CMOS Multiplexer. View full abstract»

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  • Author index

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