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Architecture of Computing Systems (ARCS), 2007 20th International Conference on

Date 15-15 March 2007

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Displaying Results 1 - 20 of 20
  • Fault-Tolerant Communication in Safety-Relevant Automotive Applications

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    More and more mechanical functions of cars will be controlled electronically. The control functions are performed by a set of controllers, which are connected by a network rather than by individuals links in cable trees. Modern cars own up to 50 ECUs (electronic control units) and separate communication systems for each region of control like power train, braking system, etc. Nowadays a typical communication system is the CAN(TM) bus. View full abstract»

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  • Repair Functions and Redundancy Management for Bus Structures

    Publication Year: 2007 , Page(s): 1 - 7
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    Predictions concerning the properties of circuits and devices fabricated in nanotechnologies indicate problems with parameter fluctuations for active devices and with the stability of interconnecting networks. While technologies that recognize and compensate transient and dynamic faults on interconnects are existing and in wide-spread use, mechanisms for built-in repair functions on interconnects have hardly been explored. This paper describes a novel scheme for built-in self repair of interconnects that can handle static and dynamic faults at reasonable overhead. View full abstract»

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  • Compression-free Checksum-based Fault-Detection Schemes for Pipelined Processors

    Publication Year: 2007 , Page(s): 1 - 6
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    We propose a fault-detection scheme for pipelined, multithreaded processors. The scheme is based on checksums and improves on previous schemes in terms of fault coverage and detection latency by not using compression but storing complete checksums from several pipeline stages. We validate the scheme experimentally and derive checksum polynomials that lead to perfect fault coverage. View full abstract»

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  • Organic Fault-Tolerant Controller for the Walking Robot OSCAR

    Publication Year: 2007 , Page(s): 1 - 5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2797 KB)  

    A robust, fault-tolerant autonomous walking robot OSCAR and its control architecture are presented. Organic Computing methods, self-organization in particular, are used to make the robot tolerant to faults of parts of itself (defective motors e.g.) or unforeseen situations it might be faced within an unstructured environment. Inspired by nature, our robot generates its gaits autonomously. In case of an injury or even the loss of one leg, OSCAR will adapt its gait to only use the remaining legs and walk ahead in a self-organizing way. We describe modifications we applied to a second prototype that allows that robot to optimize its gaits further to be able to walk also in difficult terrain. View full abstract»

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  • Fault Tolerance for Autonomous Robots by Means of Adaptive Filters

    Publication Year: 2007 , Page(s): 1 - 9
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (409 KB)  

    In this paper we discuss the effect of component faults in the legs of autonomous hexapod robots. This has been carried out by means of the simulation of the hexapod robot OSCAR developed at the University of Lÿbeck. For each of the considered fault classes, a compensating Adaptive Filter algorithm has been developed. The fault effects and their compensations are illustrated by the examples of slow motor response of a legüjoint and an improper orientation of a leg at start position of a robot trajectory. The different algorithms have been integrated to form, inside each robot leg, one coherent Leg Component Fault Tolerance Layer. View full abstract»

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  • On the Automation of Incremental Metal Forming Processes

    Publication Year: 2007 , Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (417 KB)  

    Strong tendencies towards a higher grade of individualization in consumer parts can be discovered in the automotive as well as the aeronautic industry so that the demand for individual parts has constantly increased in number over the last years. Manufacturers who have to deliver customized geometries are searching for new production strategies or try to improve the existing ones by increasing the efficiency for example by the means of automation. In this paper we will describe the status quo of the automation of driving based on kraftformer machine technology pointing out that further progress is only possible if existing failure scenarios are approached by an appropriate faultütolerant architecture. After a brief introduction to the topic from a mechanical engineering point of view we will present the current system architecture and the results that have been discovered in practice. The main focus will be set on the description of possible failure scenarios and counter measures that are subject to current research within the CoTeSysüConsortium at University of Technology, Munich. View full abstract»

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  • Reliability Prediction in Systems with Correlated Component Failures ü An Approach Using Copulas

    Publication Year: 2007 , Page(s): 1 - 8
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (619 KB)  

    We investigate, how spatial dependencies can influence the reliability of a faultütolerant system and how such dependencies may be introduced into the reliability modeL We propose the use of copulas, a mathematical dependency representation that has proven its use in other research fields such as financial risk prediction. With a Gaussian copula representation, the dependency between components in a redundant voting system is investigated. Inducing minor changes in the strength of dependency between neighbouring components, the system reliability of a voting unit varies in the order of magnitudes. View full abstract»

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  • Automatic Generation of Stateübased Dependability Models: from Availability to Safety

    Publication Year: 2007 , Page(s): 1 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (359 KB)  

    This article describes conceptual issues of the tool SafeME (The Safety Modeling Environment). The tool allows for modeling a safetyücritical, faultütolerant system. Several undiserable events like shutdown, accident, unavailability can be defined and are analyzed by within same model. Furthermore, interrelations between these events can be defined. For instance, it is possible to define that no accident can occur after an emergency shutdown. In addition, different kind of interücomponent dependencies, like failures with a common cause and failure propagation can be included. For numerical evaluation, the model is transformed into a semantically equal stateübased model. As an illustrative example, the paper contains a SafeME model of a faultütolerant temperature control system and shows how this model is converted into a stochastic Petri net. View full abstract»

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  • Experiences with Software Implemented Fault Injection

    Publication Year: 2007 , Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (194 KB)  

    The paper deals with the problem of evaluating system dependability using software implemented fault injectors (SWIFIs). In particular we describe methods of improving functionality and performance in SWIFI injectors. We discuss problems related to experiment scheduling and simulation result interpretation. The presented considerations base on our long experience with fault injection tools. They are illustrated with some practical examples. View full abstract»

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  • Elementare MutationsüOperatoren zur Generierung von Testfÿllen anhand von Statecharts

    Publication Year: 2007 , Page(s): 1 - 4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Zur Generierung von Mutanten werden in dieser Arbeit zwei BasisüOperatoren eingefÿhrt, anhand derer Mutanten erzeugt wurden. Diese können zum einen die Ereignisse und zum anderen die Zustÿnde manipulieren. Eine Fallstudie zeigt die Wirksamkeit des Ansatzes hinsichtlich der gefundenen Fehler. Weiterhin wird der Ansatz mit einem bekannten Ansatz verglichen und die durch die Basisoperatoren zu kompensierenden Mutanten herausgestellt. View full abstract»

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  • Interface Coverage Criteria Supporting ModelüBased Integration Testing

    Publication Year: 2007 , Page(s): 1 - 9
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    Even assuming exhaustive tests at component level, interaction faults can only be avoided by thorough testing of component interfaces during integration testing. In view of the relevance of the integration testing phase for modern componentübased systems, this article presents an extensive set of interface coverage criteria, which are not restricted to mere operation call sequences, but include messageübased as well as stateübased information. In order to support rational decisionümaking in identifying the best affordable integration coverage criterion for a given industrial system, a tool was implemented providing conservative estimates of the testing effort expected to be required by a given stateübased integration testing strategy considered, supporting in addition the automatic visualisation of the interface entities needed to be covered. View full abstract»

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  • Ereignisorientiertes Testen Webübasierter Systeme ü Verfeinerung des holistischen Ansatzes und eine Fallstudie

    Publication Year: 2007 , Page(s): 1 - 5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (175 KB)  

    Auf der Grundlage eines ereignisbasierten Ansatzes zum Test von Webübasierten Systemen verfeinert dieser Beitrag die Beschreibung von Eingabedaten und modelliert charakteristische Merkmale von Eingaben anhand von Eingabeformularen. Eine Fallstudie validiert den vorgestellten Testansatz unter Berÿcksichtigung von ungÿltigen Eingabedaten. View full abstract»

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  • SelfüReplication Mechanism by Means of SelfüReconfiguration

    Publication Year: 2007 , Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (210 KB)  

    Ontogenetic hardware, along with epigenetic (neural) hardware and phylogenetic (evolvable) hardware, are the key representatives of a new hardware conception paradigm known as bioüinspired hardware. Ontogenesis is the process that allows living beings to develop by means of mechanisms as growing, selfüreplication, and selfürepair. During the last few years, such ontogenetic mechanisms have been presented as a solution for the design of complex electronic circuits, with the goal of coping with the increasing complexity envisioned for future nanoütechnology devices. This paper presents an ontogenetic mechanism that allows a system, implemented in a reconfigurable device, to selfüreplicate, generating an identical copy of itself, by partially selfüreconfiguring the device containing it in a dynamic way. View full abstract»

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  • Unifying Mesh and MFPGA architectures to improve performances

    Publication Year: 2007 , Page(s): 1 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network. Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopulated local interconnect). Experimentation shows that we obtain a reduction of 14% in switches number and 2 times in the placement and routing run time. Furthermore, compared to MFPGA, the mesh of tree achieves full routability of all MCNC benchmarks since we can easily control both clusters LUTs occupation and mesh channel width. View full abstract»

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  • Design Optimisations for a Cellular Automata Model with Programmable Interconnect Structure

    Publication Year: 2007 , Page(s): 1 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (107 KB)  

    FPGA systems are often used as accelerators for software computations and can deliver speedüups of several orders of magnitude. We use such an FPGAübased system to support a genetic algorithm (GA) running in Java on a host computer to optimise cellular automata currently applied to the density classification task. Essentially, the computational intensive fitness evaluation is performed by the hardware while the GA is running as software. In this paper we concentrate on the optimisation of a programmable interconnect structure for smallüworld cellular automata and a result aggregation to reduce data transfers. The synthesis results are given and the tradeüoffs are discussed. View full abstract»

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  • Online Strategies for the Reconfiguration of TwoüLevel Reconfigurable Architectures

    Publication Year: 2007 , Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (247 KB)  

    Dynamically reconfigurable hardware offers promising possibilities for flexible, computation intensive applications. With the technological advance of reconfigurable hardware came a rapid growth in the number of resources per chip requiring large amounts of data transfer per reconfiguration. Especially run time reconfigurable applications, which make frequent use of reconfiguration, suffer from the growing overhead induced thereby. 2ülevel reconfigurable systems were proposed to reduce the amount of reconfiguration data. At the upper reconfiguration level, the reconfigurable resources that are available for subsequent lower level (ordinary) reconfigurations are determined. A prominent problem for these systems is to decide when and how the reconfiguration potential should be changed in order to minimize the total reconfiguration costs (PHC problem). Solutions to this problem have been given in the literature under the assumption that upper bounds for the reconfigurable resource demand are known in advance for all reconfiguration operations. In this paper, we study the online situation where the demand of reconfigurable resources is only known for a small number of future reconfiguration operations. Several heuristics are presented for the online version of the PHC problem. Empirical results are given where the heuristic solutions are compared to the optimal solution for the static problem. The results show that three heuristics produce very good results even when only a small number (5ü10) of future context requirements are known. View full abstract»

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  • Efficient Mapping and Functional Verification of Parallel Algorithms on a MultiüContext Reconfigurable Architecture

    Publication Year: 2007 , Page(s): 1 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (735 KB)  

    Parallel multiücontext reconfigurable architectures provide very attractive platforms with respect to computational performance and reconfigurable features. Today¿s challenge is the exploitation of this reconfigurable and computational potential to ascertain efficient solution for mapping applications onto these architectures. The demand for appropriate tools is evident. In this paper we provide a combination and a mutual adaption of two separate tools to create a continuous design flow for parallel multiücontext reconfigurable architectures. Especially we present the interaction of a parameterized mapping tool for mapping compute intensive algorithms on processor arrays and a subsequent verification of the mapping results using the Configurable Reconfigurable Core (CRC) architecture model. The SystemC implementation of the CRC model leads to a cycle accurate functional simulation of the realization. Using this continuous design flow we derive an efficient realization of the edge detection algorithm (EDA) on a parallel multiücontext reconfigurable architecture. We describe in detail how the parallel realization of the EDA has to be translated in a specification for programming the CRC model. View full abstract»

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  • Scheduling and CommunicationüAware Mapping of HW/SW Modules for Dynamically and Partially Reconfigurable SoC Architectures

    Publication Year: 2007 , Page(s): 1 - 9
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (190 KB)  

    In this paper, we present an approach for simultaneous scheduling and placement of communicating modules for SoC architectures including devices with partial reconfiguration support and at least one CPU. This approach includes (a) a detailed modeling of the communication of modules and an optimization model for finding the best temporal and spatial placement of modules on either CPU or on the reconfigurable device including communication and reconfiguration time overheads, (b) a real SoC platform for slotübased module relocation and onüchip interümodule communication called Erlangen SlotMachine (ESM), and (c) real experimental data based on experiments on this machine. Existing approaches either neglect interümodule communication, are not able to solve the related problem, or do not provide real applications implemented on real platforms. View full abstract»

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  • A Framework for the Design of Distributed Reconfigurable Embedded Systems

    Publication Year: 2007 , Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (287 KB)  

    Recent trends in embedded systems architectures are increasingly based on FPGA technologies extending traditional ASIC cores and providing reconfigurable hardware support for performance demanding applications such as multimedia and network or security processing. In this paper, we propose a new framework for the design and management of hardware reconfigurability in distributed embedded environments. The essential aim of the framework is to abstract away the details of the underlying FPGA technology and expose a register transfer level view of the hardwareüaccelerated blocks, allowing the software layer to extract, manipulate, and even export the hardware/software execution state at runütime. The paper also presents some caseüstudy scenarios emphasizing the benefits enabled by the proposed framework for the design of distributed embedded systems. View full abstract»

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  • Ethernet based inüservice reconfiguration of SoCs in telecommunication networks

    Publication Year: 2007 , Page(s): 1 - 5
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    The development of nextügeneration telecommunication infrastructure meets a number of demanding challenges. Complex functionality, highest bandwidth demands, short development cycles and dynamic market requirements are combined with emerging technologies where standardization is not complete or subject to change. This involves a high risk of errors and nonüconformances. Once the equipment is deployed, the update of chips is expensive and timeüconsuming, requiring reüspins of the devices and field exchange of circuit packs. Reconfigurable SystemsüonüChip will facilitate to accommodate changes subsequent to the deployment and thus significantly reduce failure costs. In this paper we present a new reconfiguration technology for SystemsüonüChip in a telecommunication network: design parts of deployed devices are updated based on information distributed to the SystemsüonüChip with inüband Ethernet packet streams while the network equipment stays in service. View full abstract»

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