23rd IEEE International SOC Conference

27-29 Sept. 2010

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Displaying Results 1 - 25 of 124
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Blank page]

    Publication Year: 2010, Page(s): 1
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  • [Title page]

    Publication Year: 2010, Page(s):1 - 11
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  • List of reviewers

    Publication Year: 2010, Page(s): 1
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  • Table of contents

    Publication Year: 2010, Page(s):1 - 12
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  • Author index

    Publication Year: 2010, Page(s):1 - 4
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  • Session quick index

    Publication Year: 2010, Page(s):1 - 2
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  • MPL session: Keynote/plenary session

    Publication Year: 2010, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (614 KB)

    Provides an abstract of the presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • MA3 session: SoC power optimization techniques

    Publication Year: 2010, Page(s):7 - 8
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  • Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

    Publication Year: 2010, Page(s):9 - 14
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1719 KB) | HTML iconHTML

    Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under ... View full abstract»

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  • Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors

    Publication Year: 2010, Page(s):15 - 18
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1272 KB) | HTML iconHTML

    The effective design of power distribution networks has become highly challenging with each technology generation. The power delivery network is becoming large, making the system analysis process computationally complex. The large number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distributi... View full abstract»

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  • Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation

    Publication Year: 2010, Page(s):19 - 24
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2799 KB) | HTML iconHTML

    The leakage current characteristics of wide dual Vt domino OR gates is studied and gate-level models for estimating sub-threshold leakage and gate leakage current with two different sleep states are developed to determine the optimal sleep state. Results demonstrate that the developed models are robust and exhibit maximum error of 4% with respect to device-level BSIM4 models based HSPICE simulatio... View full abstract»

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  • A run-time distributed cooperative approach to optimize power consumption in MPSoCs

    Publication Year: 2010, Page(s):25 - 30
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1390 KB) | HTML iconHTML

    Fine grain power optimization in MPSoCs architectures is now available. It is possible to independently adjust the local frequency/voltage of each processor. The objective of this work was to investigate a new system-level approach to reduce the MPSoC global power consumption at run-time. Our proposal aims to dynamically adjust the local frequency/voltage settings of each processor to save energy ... View full abstract»

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  • MB3 session: Analog 1

    Publication Year: 2010, Page(s):31 - 32
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  • Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks

    Publication Year: 2010, Page(s):33 - 38
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1736 KB) | HTML iconHTML

    Programmable switched-capacitor filters based on a cascade of programmable biquadratic sections (BQs) that use nonuniform internal clocking are described. Each section uses switched capacitors clocked a programmable number of times each sampling period without producing undesired spectral components. The clocking scheme uses a uniform input-sampling clock and provides a constant output from each B... View full abstract»

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  • A digitally self-calibrated low-noise 7-bit folding A/D converter

    Publication Year: 2010, Page(s):39 - 43
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (993 KB) | HTML iconHTML

    In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset... View full abstract»

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  • A high-resolution and fast-conversion readout circuit for differential capacitive sensors

    Publication Year: 2010, Page(s):44 - 47
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (930 KB) | HTML iconHTML

    Our readout integrated circuit (ROIC) for differential capacitive sensors, such as thin-membrane transducer, uses current switching and time-domain based technique to measure the difference between the capacitance of the sensing and reference more rapidly, while maintaining accuracy. The 12-bit ROIC is designed and fabricated in a 0.35μm digital CMOS bulk technology. View full abstract»

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  • Jitter transfer function model and VLSI jitter filter circuits

    Publication Year: 2010, Page(s):48 - 51
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1040 KB) | HTML iconHTML

    A closed form jitter transfer model is developed for modeling jitter-circuit interaction effects, such as jitter amplification and attenuation, in VLSI high-speed I/O circuits. The model is verified using circuit and behavioral simulations with good consistence. A novel jitter filtering concept and circuit is proposed to address VLSI high-speed I/O circuit performance issues. View full abstract»

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  • MT1 session: Embedded tutorial

    Publication Year: 2010, Page(s):52 - 53
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  • A holistic view on low power design

    Publication Year: 2010, Page(s): 55
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (61 KB) | HTML iconHTML

    The need for “green” systems has grown substantially over the last years. For a long time power has been a major design point mainly in the domain of handheld and battery operated devices. Driven by growing power density, rising energy cost, new legislation, environmental issues and the public awareness for it, power and energy efficiency is now more and more becoming a key different... View full abstract»

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  • MA4 session: Low power SoC circuits

    Publication Year: 2010, Page(s):56 - 57
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  • A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step

    Publication Year: 2010, Page(s):59 - 64
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1822 KB) | HTML iconHTML

    A 200MHz 10-bit pipeline analog-to-digital converter (ADC) that includes a novel multiplying digital-to-analog converter (MDAC) architecture is presented. The proposed MDAC architecture minimizes the feedback penalty, resulting more than 75% power reduction and 50% output noise reduction than those traditional architectures. The proposed MDAC dramatically reduces the settling time and operates muc... View full abstract»

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  • High speed recursion-free CORDIC architecture

    Publication Year: 2010, Page(s):65 - 70
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1850 KB) | HTML iconHTML

    This paper proposes a novel unrolled CORDIC (Co-Ordinate Rotation DIgital Computer) architecture based on parallel operations of a series of micro-rotation stages in the conventional CORDIC. To improve the speed and lower the energy consumption, a Wallace tree reduction is used for the summation of the computed parallel terms. For a large number of micro-rotation stages, a first order approximatio... View full abstract»

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  • A 1 ppm/°C bandgap voltage reference with new second-order Taylor curvature compensation

    Publication Year: 2010, Page(s):71 - 76
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (338 KB) | HTML iconHTML

    The industry's most accurate 2.5 V bandgap voltage reference is presented with true 16-bit performance: 1 ppm/C temperature coefficient, 100 μV initial accuracy, 1 μV/V line regulation and 15 μV/mA load regulation. This unique accuracy has been achieved by controlling every important parameter with a dedicated feedback loop, using unconditionally stable single-stage amplifiers... View full abstract»

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  • MB4 session: Analog 2

    Publication Year: 2010, Page(s):77 - 78
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