By Topic

3D Systems Integration Conference (3DIC), 2010 IEEE International

Date 16-18 Nov. 2010

Filter Results

Displaying Results 1 - 25 of 71
  • Content

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | PDF file iconPDF (92 KB)  
    Freely Available from IEEE
  • Welcome to the IEEE International: 3D system integration conference (3DIC)

    Publication Year: 2010 , Page(s): 1 - 16
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | PDF file iconPDF (1437 KB)  
    Freely Available from IEEE
  • 3D heterogeneous integration for novel functionality

    Publication Year: 2010 , Page(s): 1 - 19
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1476 KB)  

    Presents a collection of slides covering the following topics: 3D heterogenous integration; Moore's law; RF MEMS; antenna; TSV; carbon nanotubes; and silicon nanowires. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D integration — A server perspective

    Publication Year: 2010 , Page(s): 1 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1422 KB)  

    A collection of slides from the author's conference is presented. Topic discussed is about 3D integration from a server perspective. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D integration infrastructure & market status

    Publication Year: 2010 , Page(s): 1 - 34
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11840 KB)  

    A collection of slides for the author's conference is presented. Topic discussed is about 3D integration infrastructure and its market status. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D R&D technology for the future voyage in Japan

    Publication Year: 2010 , Page(s): 1 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4432 KB)  

    Present a collection of slides covering the following topics: 3D R&D technology for the future voyage in Japan; Moore's law limitation and possible technology solutiuons; 3DIC (dream chip) application fields: healthcare and biology, futuristic robots, advanced consumer electronics, and laptop supercomputers; communication; ubiquitous computing, autopilot for cars; capsule for inspection by CCD or CMOS camera; capsule for inspection, medication & micro operation; retinal prosthesis with 3D staked retinal prosthesis chip; structure of the human retina and 3D stacked retinal prosthesis chip; photograph of fabricated retinal prosthesis module; waveform of recorded electrical evoked potential by using Pt-b stimulus electrode; 3DIC application: automotive, sensor network, ubiquitous platform, ubiquitous platform using μ-chip, for a sustainable society; ASET dream chip project; high frame-rate image sensor; high-bandwidth memory; 3D reconfigurable device (flex chip); RF MEMS device; enabling technology: process technology, design environment, interposer technology, contact/contactless wafer probing & burn-in, and cooling and stacking/bonding; oral and poster list of ASET members; industrial structure- future; and mandatory to establish a new business scheme. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Keynote speakers day 1: 3D integration with TSV interconnects: Technology trends & market analysis

    Publication Year: 2010 , Page(s): 1 - 2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (71 KB)  

    Christophe joined Yole Développement after several positions in the wafer fab and packaging environments of CEA-Leti, STMicroelectronics and then TriQuint Semiconductor, where he has developed Wafer Level packaging technology and flipchip technology for SAW duplexers. He is now project manager at Yole for Advance Packaging, WLP & 3D system Integration and RF devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cost effectiveness of 3D integration options

    Publication Year: 2010 , Page(s): 1 - 6
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    The available manufacturing options for 3D integration have different impact on the cost of a 3D-stacked system. Using the 3D cost model developed at imec, the cost of different technology integration options is analyzed and the cost effectiveness of different technology solutions is compared. The cost model is based on imec's 3D integration process flows and includes the cost of manufacturing equipment, fabrication facilities, personnel, and materials. A breakdown of different 3D processing steps into these costs is presented. Furthermore, the effect of different TSV geometries on system manufacturability and cost is investigated. The effectiveness of different TSV redundancy and repair approaches is evaluated and their impact on system cost is also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fine-pitch bump-less Cu-Cu bonding for wafer-on-wafer stacking and its quality enhancement

    Publication Year: 2010 , Page(s): 1 - 5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB) |  | HTML iconHTML  

    3D integration by means of face-to-face (F2F) stacking of wafer-on-wafer (WoW) is successfully demonstrated using bump-less Cu-Cu bonding on 200 mm wafers. Cu surface topology is optimized and carefully cleaned prior to bonding. Bonded Cu structures provide sufficient mechanical strength to sustain shear force during wafer thinning. Excellent specific contact resistance of ~0.34 Ω.μm2 is obtained. The contact resistance is attributed to the formation of micro-voids at the bonding interface. Continuous daisy chain contains at least 16,000 contacts at 15 μm pitch is connected successfully. This provides IC-to-IC connection density of 4.4 × 105 cm-2 suitable for future wafer level 3D integration of IC to augment Moore's Law scaling. Finally, a non-vacuum and non-corrosive method to provide temporary passivation of Cu using self-assembled monolayer (SAM) is described and improvement in the Cu-Cu bond quality is presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Manufacturing service on 3D ICs

    Publication Year: 2010 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3DIC multi-project-wafer program: A collaboration to provide fabrication access

    Publication Year: 2010 , Page(s): 1 - 17
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1317 KB)  

    A collection of slides from the author's conference presentation is given. The following topics are discussed: 3DIC multiproject-wafer program; CMP/CMC/MOSIS; MOSIS multiproject wafer; Tezzaron 3DIC technology; silicon workbench for photonics; and silicon workbench for MEMS and III-V compound semiconductors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design platform and tools for 3D IC integration

    Publication Year: 2010 , Page(s): 1 - 25
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2761 KB)  

    A collection of slides from the author's conference presentation is given. The following topics are discussed: design platform features, 3D-IC integration, 3D-IC automatic place & route. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The NCSU Tezzaron design kit

    Publication Year: 2010 , Page(s): 1 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A collection of slides from the authors' conference is given. Topics include NCSU design kit user guide, Verilog memory model, and lessons learned in assembling the reticle. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and Tezzaron

    Publication Year: 2010 , Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1036 KB)  

    Presents a collection of slides covering the following topics: 3D IC multiproject fabrication; high energy physics; circuit bonding; wafer thinning; TSV; radiation detector; CMOS; wafer bonding; and SOI process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D ICs and pixel sensors: The Italian VIPIX project and the European AIDA WP3 project

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (382 KB)  

    Presents a collection of slides covering the following topics: 3D integrated circuits; pixel sensors; Tezzaron vertical integration technology; microelectronics; and interconnection technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D motivations for high energy physics

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (169 KB)  

    A collection of slides from the author's conference presentation is given. The following topics are discussed: 3D IC; high energy physics; hybrid pixel community; imaging device; and MAPS community. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High sensitivity fully digital photodetector

    Publication Year: 2010 , Page(s): 1 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    A collection of slides from the author's conference presentation is given. The following topics are discussed: fully digital photodetector; instrumentation for medical imaging; electronic flow; 3D stack-up; and 3D IC design in tezzaron technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Post-bond sub-500 nm alignment in 300 mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si fusion and oxideoxide fusion bonding

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    We report recent advances in tool and process hardening of a first of its kind 300 mm wafer-to-wafer (WtW) preprocessing, aligning, and bonding integrated tool. We have demonstrated sub-500 nm post-bond alignment accuracies for 300 mm WtW face-to-face (FtF) Cu-Cu thermocompression bonds, WtW FtF Si-Si fusion bonds, and WtW FtF oxideoxide fusion bonds. All process of record (POR) recipes that were developed had undetectable voids based on scanning acoustic microscope (C-SAM) measurements on representative bonded Cu, oxide, and Si blanket wafers. Optimized bonded patterned wafer splits in the Cu-Cu WtW thermocompression bonding step have shown alignment accuracies down to ~190 nm, the highest accuracy to date. Using an infrared-enabled, high speed focused ion beam (FIB) system (with XeF2) with a CAD overlay function to assist in selective sample preparation, we have verified that the bonding interfaces at the via chain structures with 1-5 μm diameter vias show no interfacial voids. Also, there is evidence of Cu interdiffusion, as supported by transmission electron microscopy (TEM) and electron backscattering diffraction (EBSD) data. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and early evaluation of a 3-D die stacked chip multi-vector processor

    Publication Year: 2010 , Page(s): 1 - 8
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB) |  | HTML iconHTML  

    Modern vector processors have significant advantages over commodity-based scalar processors for memory-intensive scientific applications. However, vector processors still keep single core architecture, though chip multiprocessors (CMPs) have become the mainstream in recent processor architectures. To realize more efficient and powerful computations on a vector processor, this paper proposes a 3-D stacked chip multi-vector processor (CMVP) by combining a chip multi-vector processor architecture and the coarse-grain die stacking technology. The 3-D stacked CMVP consists of I/O layers, core layers and the vector cache layers. The I/O layer significantly improves off-chip memory bandwidth, and the vector core layer enables to install many vector cores on a die. The vector cache layer increases the capacity of on-chip memory and a high memory bandwidth to achieve the performance improvement and energy reduction by deceasing the number of off-chip memory accesses. The results of performance evaluation using real scientific and engineering applications show the potential of the 3-D stacked CMVP. Moreover, this paper clarifies that introducing the vector cache is more energy-effective than increasing the off-chip memory bandwidth to achieve the same sustained performance on the 3-D stacked CMVP. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High performance 3D interconnects based on electrochemical etch and liquid metal fill

    Publication Year: 2010 , Page(s): 1 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (819 KB) |  | HTML iconHTML  

    Besides the usually known TSV technologies to etch and fill Si interconnects there is a powerful photo-assisted electrochemical etch technology for fine pitch TSV, which goes hand in hand with a liquid fill metallization. Both together allow the generation of high density wiring on and through thick self-carrying interposers, where other technologies fail. Together with any etching technology the liquid fill technology allows an extremely simple process flow to realize conductor lines inside buried channels. Taking the right material combinations there is very low stress inside the substrate, which allows a high design freedom for larger via or systematic aligned via. Using the fill technology for stacked dies an extremely simple and compact 3D wiring is possible. It is less complex than conventional ones since it does not need any seed layer or additional balls between chips. The fill technology has the potential of complete wiring of multichip systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3D DfT architecture for pre-bond and post-bond testing

    Publication Year: 2010 , Page(s): 1 - 8
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1291 KB) |  | HTML iconHTML  

    Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as post-bond stack testing of both partial and complete stacks. The architecture enables on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow flexible optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1500 or IEEE Std 1149.1. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic-on-logic 3D integration and placement

    Publication Year: 2010 , Page(s): 1 - 4
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB) |  | HTML iconHTML  

    In this paper we describe three 3D standard cell placement algorithms, which are: “3D Placement using Sequential Off-the-Shelf 2D Placement Tools”, “True-3D Analytical Placement with mPL” and “3D Placement using Simultaneous 2D Placements with mPL”. We use these algorithms to place three case studies in a real face-to-face 3D integration process. The three case studies are a 2 point FFT butterfly processing element (PE), an Advanced Encryption Standard encryption block (AES) and a multiple-input and multiple-output wireless decoder (MIMO). The placements are then fully routed and compared to 2D placements in terms of performance and power consumption. Using this methodology we show that using 3D face-to-face integration with microbumps in conjunction with the three placement algorithms we can improve the maximum clock speed of AES module by 15.3% and the PE by 22.6%, while reducing the power of the AES module and the PE by 2.6% and 12.9% respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications

    Publication Year: 2010 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB)  

    In a 3D chip stack, it is important to thermally isolate any DRAMs from high power processors, so that the former can operate at low junction temperatures. One way to do this is to use the combination of a vacuum gap, formed using standard semiconductor processing, together with capacitive or inductive signaling across the gap. Simulation shows that the DRAM can operate at a temperature 47°C cooler than the CPU. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding

    Publication Year: 2010 , Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB) |  | HTML iconHTML  

    Micro-Raman spectroscopic technique has been employed to study the induced stress/strain by the metal microbumps in 3D-LSI Si die/wafer after wafer thinning and bonding, and the impact of bump spacing, bump size, bonding temperature and bonding force in the stress distribution in such a microbump bonded LSIs has been investigated. It is inferred that (i) the Si present at the interface (between CuSn and LSI die/wafer) is under compressive stress, and it decreases exponentially in the cross-sectional direction both in the die and the wafer; (ii) in the lateral direction, the compressive stress produced by the adjacent microbumps overlapped to each other at the region of bump-spacing; (iii) qualitatively, the residual mechanical stress/strain increases with the bonding temperature and the size of the microbump, i.e. it is large for the higher bonding temperature (as high as >;300 MPa @300°C) than for the non-bonded microbump (a maximum of only +125 MPa @ 280°C); (iv) the metal microbump exerted a large compressive stress up to the depth of >;10 μm in the bonded 3D-LSI die/wafer. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Enabling power distribution network analysis flows for 3D ICs

    Publication Year: 2010 , Page(s): 1 - 4
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (95 KB) |  | HTML iconHTML  

    This paper concentrates on some of these new challenges that designers must face in power delivery. We will discuss QUALCOMM's effort with EDA vendors to develop power distribution network (PDN) analysis flows in order to address the power delivery issues in 3DICs, and emphasize the necessity of a standard reduced power model (SRPM) to enable the 3D PDN analysis flows. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.