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Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International

Date Nov. 30 2010-Dec. 2 2010

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Displaying Results 1 - 25 of 115
  • [Title page]

    Publication Year: 2010 , Page(s): 1 - 25
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  • Investigation of bond pad etching chemistries for passivation crack

    Publication Year: 2010 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (919 KB) |  | HTML iconHTML  

    Wire bonding is still a very common method for connecting the pads on a chip to the package. During the ultrasonic wire bonding process, several failures such as ball neck failure, missing ball, bond metal peeling or crack etc., may be generated. Of those failures, bond pad peeling or crack is a phenomenon detected after bonding process and is identified as a critical reliability problem and is known as a complex defect to investigate. Bond pad cracks pose a high reliability risk and potential failure during environmental stress testing. Damage to the bond pad may be the result of sub optimized probe or wirebond process parameters, as well as poor pad design. In addition, bond pad cracks may be unintentionally induced by the cratering test chemical etch solution. There is a case where an assembly folk reported had a bond pad crack, but none of the parts have failure during electrical test or even after reliability stress. In such case, we believe the crack found at assembly was an artifact induced by etching chemical, resulting the over-rejecting the parts. This paper specifically discusses a comparative analysis of various bond pad etching methods and their impact on bond pad cracking. There are few interesting findings will also be shared during the discussions. Failure analysis results are also briefly discussed. View full abstract»

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  • Investigations of the effects of blade type, dicing tape, blade preparation and process parameters on 55nm node low-k wafer

    Publication Year: 2010 , Page(s): 1 - 6
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1459 KB) |  | HTML iconHTML  

    This paper presents an investigation of the effects of blade type, dicing tape, blade preparation and the key process parameters optimization on improving topside ILD peeling (thicker scribe structures) and chipping for 55nm low-k wafer. An appropriate dicing blade selection, blade preparation / conditioning methodology and dicing tape selection plays an important role in developing a robust saw process. As such, experimental studies were conducted under varying Z1 spindle rotation, Z1 cut depth into Si as well as the blade type property variation as the input factors, in order to improve the ILD peeling and die chipping. The settings of machining parameters and blade types were determined by using the design of experiment (DOE) techniques and the critical process parameters and materials were analyzed statistically by using the analysis of variance (ANOVA). Dicing tape property variations (PO-base or PVC-base) as well as the blade preparation methodology posed some influences on the overall dicing quality, such as die backside chipping, die removal performance, ILD peeling and die topside chipping. SEM imaging and optical visual inspection were conducted to validate the impacts of the ILD peeling / chipping on post-processed low-k wafers. A thorough quantification and categorization of ILD peeling and chipping on heavy metallization at the saw scribe structures were described. As part of the recommendation for future works, a different approach in dicing technology, namely laser grooving was proposed to eliminate ILD peeling and chipping. In conclusion, the optimized dicing recipe for 55nm node low-k wafer suggested by the DOE model are: (1) a thinner PO-base dicing tape, (2) a dicing blade with higher diamond concentration and finer grit size, (3) blade preparation / conditioning done with SiC board and (4) processing at lower spindle rotation and deeper cut depth are much preferred. The overall dicing responses and cutting quality has improved and is better compa red to current production recipe. View full abstract»

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  • Development of wafer sawing capability on 2 mil saw street 4 mil thickness with TiNiAg back metal

    Publication Year: 2010 , Page(s): 1 - 6
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    For existing industrial trend, increasing the Potential Die per Wafer (PDPW) through saw street reduction has become the common practice for wafer manufacturing cost reduction, which meant that sawing on wafer with saw street as narrow as 2 mil has become an important wafer sawing process in the market. The sawing process is becoming more complex with the requirement of multi layer wafer back metallization, such as TiNiAg. This paper reports the successful of development of wafer sawing capability on 2 mil saw street 4 mil thickness with TiNiAg Back Metal. The success of this sawing capability has created the opportunity not only for wafer cost reduction, but also provides a solid base and reference for the development of more challenging sawing process in future. This paper describes the development of the sawing capability. View full abstract»

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  • Impacts to fine pitch copper wire bonding quality by external airflow

    Publication Year: 2010 , Page(s): 1 - 5
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    Smaller diameter Cu wire has been incorporated in actual volume production and migrated into fine pitch IC packages in the past few years. Copper is easily oxidized by forming copper oxide that will hinder the welding process between copper to Aluminum bond pad surface. Forming gas must be used to protect the copper from reacting with oxygen for this reason. Intensive studies that focused on EFO parameter, inert gas flow rate and wire types were mainly conducted to achieve robust FAB (free air ball) process in the past. The key for a reliable finer copper ball process is not only the formation of defect-free FAB during EFO sparks stage but slight oxidation during search stage and bonding stage shall not be neglected. This paper discusses the issues and challenges encountered during the development of ultra fine copper ball. It also covers the impacts to the quality of ultra fine copper balls by possible oxidation during search stage, bonding stage and external air flow or air turbulence. Performance and resistance to disturbance by external air flow using different nozzles design from ASM are also compared in this paper. View full abstract»

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  • Ultra low loop conversion from gold to copper wire

    Publication Year: 2010 , Page(s): 1 - 5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (547 KB) |  | HTML iconHTML  

    It has been a trend to convert gold wire to copper wire in manufacturing of semiconductor chip due to cost effectiveness. Another motivation for the conversion comes from the physical properties of copper wire. Copper wire offers the advantages of presenting higher mechanical strength, lower electrical resistance and slower intermetallic growth. Aside from the differences in term of chemical stability, copper is a stiffer material as compared to gold. It has been determined that copper wire requires new process optimization in comparison to gold wire. Parameter adjustments for ball bond formation, stitch bond formation, and looping profile are needed during conversion from gold to copper. It is challenging to convert a loop profile from gold to copper wire, especially for the case of ultra low loops with a loop height of 3 mils and lower. Wire humping is the main challenge to be faced on copper wire. Loop profile configurations are determined physically by die thickness, wire length, and other package requirements. Total conversion of loop shape and loop height from gold wire to copper wire involves complex processes. It may not be realistic, nor functionally required, to replicate the exact loop shape in actual implementation. However, the aim is to retain the same loop height while not significantly changing the loop shape. Copper wire also seems to have a higher tolerance than gold in terms of neck damage. This allows users to have a wider setting of parameters related to the wire neck. In term of process application, ultra low loop copper wire is comparable to gold wire after optimization. View full abstract»

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  • Integrated nCTF pad design on PCB for BGA solder joint reliability enhancement

    Publication Year: 2010 , Page(s): 1 - 4
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    In PCBA manufacturing industry, corner adhesive was commonly used on BGA(Ball Grid Arrays) to resolve the solder joint crack induced by mechanical stress either during shock and vibration reliability test or during board manufacturing processes(ICT test fixture, router, handling and etc) especially for mobile motherboard. However, this solution imposed high manufacturing cost which required additional glue processes with more process control, additional equipment setup for adhesive dispenser and curing oven as well as additional material cost for the adhesive. Besides that, the BGA with corner adhesive is difficult to be reworked especially for high-temperature curing adhesive. A new approach in PCB design for BGA called integrated nCTF(non critical to function) or dummy pad has been developed to replace the costly corner adhesive to address the problem of solder joint crack induced at post board level shock and vibration reliability test as well as time-0 solder joint crack induced by mechanical stress during board manufacturing. This paper will review the land pattern of the integrated nCTF pad design, stencil opening design, evaluation plan and the results of CTF(critical to function) solder joint crack percentage comparison between integrated nCTF pad and individual nCTF pad as well as to show the bulky solder joint formed on the integrated nCTF pads. View full abstract»

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  • 2nd level reliability drop test robustness for Wafer Level Packages

    Publication Year: 2010 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1093 KB) |  | HTML iconHTML  

    2nd level reliability performance during drop impact is critical for Wafer Level Packages (WLP). Accompanying the popularization of portable and mobile phone products, high reliability under board level drop test is a great concern to semiconductor manufacturers. A 0.4mm pitch Cu under bump metallization (UBM) type has been developed for mobile computing application. In this paper presents the impact on solder joint reliability with various approaches to achieve higher Drop Test (DT) robustness. Polymer Core solder ball, solder ball Sn1.2AgCu (additive Ni + α), polymer flux with SAC107 solder ball, solder ball Sn1.2Ag0.5Cu (doped), copper core solder ball, and additional 6μm passivation layer (polyimide) have been investigated. The test vehicles were 49 pins and 0.4mm ball pitch with Cu UBM. Ball shear test was carried out to measure the solder joint performance after reflow process and units were performed cross sectioned for IMC formation analysis. Board level drop test was performed as per JESD22-B111 test method. The drop test results showed polymer core solder ball gives the best performance which is more than 1000 drops, followed by Sn1.2Ag0.5Cu (doped) solder ball, polymer flux, additional 6um polyimide, Sn1.2AgCu (additive Ni + α) solder ball & copper core solder ball. It indicated the stress relaxation within IMC & strength improvement to achieve higher drop test performance for polymer core solder ball during drop test. On the other hand, copper core solder ball has the worst drop performance (66 drops) as it has rigid material (Cu) inside the ball and less solder amount that can absorb the drop impact and stress. View full abstract»

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  • Effect of convection and conduction oven to the intermetallic formation and solder joint reliability

    Publication Year: 2010 , Page(s): 1 - 5
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    This paper presents the effect of the reflow oven type to the intermetallic (IMC) formation and solders joint reliability for the wafer level packages (WLPs). Two common used reflow oven in electronic manufacturing industry which are conduction and convection oven have been studied. Four reflow profiles with same peak temperature and wetting time for both ovens were developed. In this study, two low (240°C) and high (255°C) peak temperature were investigated. SAC107 solder ball with Cu UBM pads of WLP daisy chain were reflowed by using each ovens. The formation of IMC was observed at the interface of the solder and Cu UBM pad and found that oven type is significantly influence the IMC formation. The reflow profile for convection oven produced longer IMC needles and visible over the whole UBM pad. On the other hand, IMC needles are only visible at the perimeter of the pad for the conduction oven. Drop Test (DT) and Temperature Cycle Test (TCT) were used to evaluate the solder joint reliability. From the board level test results, solder balls reflowed by convection oven have achieved better thermal performance than conduction oven. Failure analysis was performed on the TCT units and found that crack line propagated in the solder bump but not in the IMC layer as the IMC needles acts as a barrier to crack propagation. With the 25% improvement in TCT performance by convection oven, Infineon Technologies is now exceeding customer expectation and sustaining competitive advantage in WLP market. View full abstract»

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  • No-clean polymer flux evaluations and its impact on BGA solder joint quality and board level reliability

    Publication Year: 2010 , Page(s): 1 - 7
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    In the automotive industry, electronic systems are expected to perform well under harsh reliability conditions. There is an emphasis to continuously develop ball grid array (BGA) IC packages that perform increasingly well with respect to board level temperature cycling reliability. This paper is a study of three No-Clean Polymer Flux (NCPF) materials and evaluation of their performance relative to a standard water-soluble flux. The study was targeted to evaluate NCPF's effect on processability, package ball grid array (BGA) solder joint quality and more importantly, its effect on temperature cycling reliability on board. Results showed that NCPFs generally performed comparatively on par or better than standard water-soluble flux. The NCPF variant selected for board level temperature cycling reliability test proved to have a positive impact in improving BGA solder joint reliability. View full abstract»

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  • Progressive damage in Sn-4Ag-0.5Cu solder joints during flexural fatigue of a BGA package

    Publication Year: 2010 , Page(s): 1 - 5
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    This study examines evolution characteristics of inelastic strains and materials damage in Sn-4Ag-0.5Cu (SAC405) solder joints of a BGA package under cyclic mechanical stressing. For this purpose, a finite element model of the assembly under four-point bend test set-up is employed. Strain rate-dependent response of the solder is represented by Anand model. Progressive damage in the solder joint is described using continuum damage model. Results show that the critical solder joint is the one located at the corner of the BGA package. In this critical solder joint, both high stress and inelastic strain are localized in a small edge region at the solder/IMC interface at the board side of the assembly. The different inelastic strain rates experienced by the critical solder joint during fatigue cycles correspond to the distinct damage initiation stage, crack propagation stage and the final fast fracture of the solder joint. Damage initiation life covers nearly half of the total fatigue lives of the critical solder. View full abstract»

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  • Alternative robust reliability solution for silver finishing

    Publication Year: 2010 , Page(s): 1 - 6
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    In this paper, a silver adhesion promoter process, namely “AgPrep” was introduced for the semiconductor leadframes. The concept of how AgPrep works to improve the adhesion between the silver surface of a leadframe and the epoxy molding compound (EMC) was presented. X-ray Photoelectron Spectroscopy (XPS) analysis was also carried out to study the chemical state of the silver surface after AgPrep's treatment. Besides, the surface energy of AgPrep's treated silver was characterized through the contact angle measurements using a drop shape analyzer. Finally, the adhesion performance of AgPrep process was verified in the button shear tests and a series of reliability tests. View full abstract»

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  • Electroless over pad metallization for high temperature interconnections

    Publication Year: 2010 , Page(s): 1 - 7
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2958 KB) |  | HTML iconHTML  

    Electrolessly plated over pad metallization (OPM) was evaluated for high temperature gold wire bonding applications. Bonding strength, measured by wire bond bump shear test, of 4N gold wire on electroless OPMs, such as electroless nickel/immersion gold (ENIG), electroless nickel/electroless palladium (ENEP), and electroless nickel/electroless palladium/immersion gold (ENEPIG), was carefully evaluated before and after wire bond was subjected to various environmental stresses. Failure modes, besides bonding strength, were particularly examined for overall bonding quality assessment and OPM screening. Authors' intensive work found that ENEPIG OPM had the highest bonding strength and consistent failure mode over the other two OPM options: ENIG and ENEP. Even after 3000 hours of 175°C high temperature storage life test, there is no sign of bonding strength degradation. Processes of ENIG, ENEP and ENEP1G OPMs were compared, in conjunction with pros and cons of each OPM choice. Plating imperfections, found in almost every ENEP1G OPM cross section, are also discussed in details. View full abstract»

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  • Adaptation of brass core lead frame material in IC packaging

    Publication Year: 2010 , Page(s): 1 - 4
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    In today's lead frame IC packages, the cost of lead frames account for one of the largest portion of material costs. Etched lead frames can cost 50% of the total package cost where as stamped frames can cost around 30%. With the increasing price trend of raw copper material in recent years, fueled by increasing demand on the use of copper (e.g. as an Au bonding wire replacement) this will inevitably impact the cost of high copper purity core lead frame. It will add a significant cost to the total package cost. Therefore an alternative, cheaper leadframe material is very much needed to keep the total packaging cost down. This paper will report the investigation of the use of brass core material as an alternative replacement to high purity copper alloy lead frame. General cost advantages, technical challenges and assembly feasibility on the use of brass core lead frame material are assessed and discussed. Reliability assessment will only be done in our next phase of investigation. View full abstract»

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  • Solving eventual bonding quality to enhance adhesion for QFN packages

    Publication Year: 2010 , Page(s): 1 - 6
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    Many of the components used extensively in today's handheld market are beginning to migrate from traditional lead frame design to leadless or non leaded. The primary driver for handheld manufacturers is the saved PC board space created by these components' smaller mounting areas. In addition, most components also have reductions in weight and height, as well as an improved electrical performance. As critical chip scale packages are converted to non-leaded designs, the additional space saved can be allocated to new components for added device functionality Similar to leaded components, nonleaded designs use wire bond as the primary interconnection between the IC and the frame. However, due to the unique land site geometry and form factor density, traditional wire bond processes may not produce high yielding production. For these designs, additional wire bond capabilities and alternate processes are needed to produce acceptable production yields. This paper discusses the eventual challenges of wire bond for QFN package designs and describes how new wire bond capabilities and process optimization can improve production yields but on top of the impact need to be consider as well during the higher force impact which could deteriorate the looping profile on the adjacent wire. The advantages of the conversion of the design which could improve the conversion rate on the production. View full abstract»

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  • Interfacial reactions of SAC305 and SAC405 solders on electroless Ni(P)/immersion Au and electroless Ni(B)/immersion Au finishes

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2300 KB) |  | HTML iconHTML  

    The formation of intermetallic compounds (IMCs) on solder pads is strongly affected by the type of PCB surface finish since different finishes may lead to several different interfacial reactions and IMCs formation. Since the joint reliability is also determined by the type of the interfacial IMC layer between the solder and substrate, understanding how such intermetallic compounds form and grow during soldering and subsequent thermal ageing is essential. In this paper, experimental results of the effect of three different surface finishes namely: electroless nickel (phosphorus)/immersion gold, electroless nickel (boron)/ immersion gold and bare copper (for comparison) on the formation and growth of interfacial reactions during soldering and thermal ageing with Sn-3Ag-0.5Cu and Sn-4Ag-0.5Cu solders are presented. Several techniques of materials characterization including optical, image analysis, scanning electron microscopy and energy dispersive X-ray analysis were used to examine and quantify the intermetallics in terms of composition, thickness and morphology. The results showed that after soldering on Ni-Au finishes the reaction layer was found to consist of only one layer of (Cu, Ni)6Sn5 with a needle-shape morphology. In addition, the results from SEM with energy dispersive x-ray (EDX) have revealed that isothermal aging at 150°C has caused the thickening and coarsening of IMCs as well as changing them into more spherical shape. During soldering on Ni(B)/Au finish it was observed that closer control of the reflow temperature was very important compared to soldering on Ni(P)/Au finish. Selective etching of solder joints also revealed that the morphology of the intermetallic formed is different across a single solder joint from the centre to the outside edge. View full abstract»

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  • Meeting the assembly challenges in new semiconductor packaging trend

    Publication Year: 2010 , Page(s): 1 - 5
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    Semiconductor packaging is being driven by the market requirement for an increase in operating speed and higher functional density, which requires chip makers to develop more sophisticated packaging to meet this trend. On the other hand, there are demands for the package to be smaller, thinner and less expensive, imposing tremendous challenges on chip manufacturers to meet compelling assembly to meet assembly challenges in this new packaging technology. As technology grows, the demand for new packages with even greater sophistication will drive package innovation. The purpose of this paper is to describe the potential challenges that encounter during assembly process, material selection and characterization in order to manufacture a product that has a low profile, high functionality, and low cost, green and reliable package for molded leadless packages. The challenges will include assembling the molded lead less package with multiple types of epoxy, wires and chip and at the same time shrinking the total package dimensions in order to meet the market requirement. Selection of material both direct and indirect material are also crucial. Any material CTE mismatches makes moisture performance more difficult to achieve. View full abstract»

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  • Plasma process considerations in emerging semiconductor packaging technologies

    Publication Year: 2010 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (283 KB) |  | HTML iconHTML  

    Plasma cleaning technology is a well known method of contamination removal and surface activation to enhance the performance and reliability of advanced semiconductor packages. It has also gained widespread acceptance and implementation over the last 10 years. With the continued introduction of new packaging technologies and materials, the applications for plasma technology have also broadened. This paper will review the considerations and performance benefits of employing plasma technology in flip chip, copper wirebonding and LED lens molding applications. The importance of using the optimum combination of process parameters and plasma technology in conjunction with different combination of materials will be the key underlying theme. This will be clearly illustrated firstly with a flip chip application example where the correct gas chemistry is shown to be important in achieving the desired adhesion and reliability characteristics in a flip chip underfill process. Quantitative data obtained from field studies will also be presented to show how plasma treatment can enable the realization of the low-cost benefits of copper wirebonding. Also discussed will be how the advantages of inline type plasma over a batch type system can produce significantly improved wirebond results. Finally, we will discuss how the adhesion promotion ability of plasma treatment enables the high-volume, low cost production of molded silicone LED lenses. View full abstract»

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  • Fabrication of silica/epoxy thin film composite for electronic packaging application

    Publication Year: 2010 , Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    Conventional packaging technology has been replaced in line with the miniaturization trends of the product designs in electronic industry. A polymer resin needs to suit to certain polymer processing methods in order to achieve substantial performance in terms of mechanical, thermal, optical, electrical and so forth. In this study, an epoxy based thin film composite was successfully fabricated by using the spin coating method. Comparing this with the conventional method such as dip coating, solution casting and hot pressing methods, spin coating fabrication method allows controllable-uniform thickness ranging from micron to nanometer. In order to enhance the thermal, mechanical and its dimensional stability, two types of silica fillers which are in micron and nano-sized were studied. The nano-sized silica was found to further enhance the properties of the epoxy thin film at low weight fraction. This is due to its higher ratio of surface area to volume compared to the micron-sized silica. View full abstract»

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  • Keep on shrinking interconnect size: Is it still the best solution?

    Publication Year: 2010 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1394 KB) |  | HTML iconHTML  

    According to the evolution between each new technological generation of CMOS ICs, ITRS suggests a reduction in interconnect sizes by a factor of around square root of 2. In this paper a reference design rule is based on a perfectly controlled technology of the CMOS 45 nm node, with interconnects width equal to their separation space. Our works are focused on the impact on signal transmission speed and delay along interconnects of decreasing the space or width. To avoid new industrial manufacturing constraints on cost and reliability, this study is performed without modifying process and materials used in the BEOL of CMOS 45 nm IC. We will study interconnects of 50 nm width, with a 50 nm space between lines in accordance with CMOS 32 nm FEOL requirements. In the second time we will relax geometrical constraints to enlarge the scope of application. View full abstract»

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  • 3D Packaging Technology: Enabling the next wave of applications

    Publication Year: 2010 , Page(s): 1 - 5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1927 KB) |  | HTML iconHTML  

    This paper describes 3D Packaging Technology trend and highlights its contribution to the development of the next wave of electronic products. The paper's introduction discusses general Packaging Technology trends in the semiconductor industry and the major Packaging Functionality changes that have been experienced during the last few decades. It also covers some of the future functions that will be performed by packaging technology such as system in packages to enable autonomous smart electronics, with heterogeneous technology such as signal processing, sensors, power management, energy harvesting modules and nano storage devices. It describes the evolution of 3D packaging technology in three different waves or phases. It also presents some of the Megatrends enabled by 3D Packaging, Miniaturization and Integration, as well as the main challenges the industry is experiencing with the development and implementation in volume production of the third wave, Through Silicon Vias (TSV). The final section of this paper discusses TSV drivers and benefits, the expected Value Added coming from TSV vs. Required Cost to Develop and Implement, and whether TSV is going to be used in mostly “Niche High Value Added” applications or adopted as a Mainstream solution for many applications. View full abstract»

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  • Chipping free process for combination of narrow saw street (60um) and thick wafer (600um) sawing process

    Publication Year: 2010 , Page(s): 1 - 5
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1206 KB) |  | HTML iconHTML  

    Chipping free is a dream for wafer sawing process. With current high complexity of wafer technology plus the drive for cost reduction by narrowing the saw street width, it is a challenge which requires huge effort for wafer sawing process to achieve chipping free process. Higher density of metallization causing higher blade loading during mechanical sawing. This leads to chipping penetrating under the guard ring and damaging the active area. This paper will share all the activities towards chipping free process on a device involving optimization through mechanical sawing, infra red camera and laser grooving process. Blade selection involving various diamond grit size, different concentration, slit design and low k types only able to minimize the occurrence but not totally eliminate it. Finally by performing laser grooving, significant results were achieved with zero chipping occurrences. In addition, suitable laser frequency selection is also important to ensure the best performance. In this case higher frequency laser grooving in combination with mechanical sawing process found to be able to meet the requirement. View full abstract»

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  • Alternative dicing die attach film method for high volume small dice application

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    This paper introduces an unconventional sawing approach for sawing die attach film (DAF) to successfully re-solve severe loose dies and severe dies non-pick issues at die attach (DA) process particularly small dice application. Conventional forward step cut during DAF sawing causes the DAF layer to penetrate and anchor into the base/dicing film. A diverse wafer sawing approach and study on DAF was carried out by evaluating different sawing method and sawing parameters. The results show that for small dice DAF sawing, a modified step reverse cut mode is crucial to ensure good and high die attach pick up yield. An innovative reverse step cut sawing method is proposed for sawing small dice application with DAF. View full abstract»

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  • Thermal simulation study of die attach delamination effect on TQFP package thermal resistance

    Publication Year: 2010 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB) |  | HTML iconHTML  

    Delamination in semiconductor plastic packages often happens in many interfaces within the package itself, which is mainly caused by coefficient of thermal expansion (C.T.E) mismatch between the interfaces of two materials within the package. Die attach delamination is the separation between the silicon die and die attach pad on leadframe. Die attach delamination will reduce the total area of silicon die attached to pad and it is known to have increase the thermal resistance of the package. This could lead to early thermal shutdown of a device which uses exposed pad to dissipate heat. This paper is to investigate the die attach coverage effect on the package thermal resistance. A thermal modeling was done on various % of epoxy coverage to evaluate package thermal resistance. TQFP 100L with and without exposed pad are used for this model. Results show that die contact area to the pad will significantly affect the package thermal performance, especially at high power application. Package with exposed pad design will have higher increase of θja than non exposed pad in the event of die attach delamination. View full abstract»

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  • High-speed vision challenge for 100% online on-Strip inspection

    Publication Year: 2010 , Page(s): 1 - 6
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    The paper presents the challenges of effective high-speed detection for screen out incomplete fill (IF) reject via online Vision System at Trim/Form process. In general, most of the assembly factories screen the incomplete fill reject manually or through a vision on Test Handler. The speed of this Unit by Unit inspection is very low. Usually, the effective UPH is less than 30k. Accordingly, a new idea of online Strip by Strip inspection is bring out. By this way, total 36 units (or even more) can be detected every step. And the inspection UPH can reach to more than 500k. To achieve this target, the biggest challenge comes from that large image data/information need to be processed in tens of microseconds. As presented in this paper, based on advanced algorithms, excellent program structure and optimized hardware composition, the system can realize 100% online unit inspection with only 1 camera at a Trim/Form machine. The speed of this vision can freely match with any high-speed running Trim/Form machine, which will gain competitive advantages. View full abstract»

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