By Topic

Design and Test Workshop (IDT), 2010 5th International

Date 14-15 Dec. 2010

Filter Results

Displaying Results 1 - 25 of 52
  • Final program

    Publication Year: 2010 , Page(s): 1 - 5
    Request Permissions | PDF file iconPDF (74 KB)  
    Freely Available from IEEE
  • [Title page]

    Publication Year: 2010 , Page(s): i
    Request Permissions | PDF file iconPDF (699 KB)  
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2010 , Page(s): ii
    Request Permissions | PDF file iconPDF (22 KB)  
    Freely Available from IEEE
  • Welcome message from the chairs

    Publication Year: 2010 , Page(s): iii
    Request Permissions | PDF file iconPDF (47 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • IDT'10 Committees

    Publication Year: 2010 , Page(s): iv - v
    Request Permissions | PDF file iconPDF (61 KB)  
    Freely Available from IEEE
  • [Blank page]

    Publication Year: 2010 , Page(s): vi
    Request Permissions | PDF file iconPDF (5 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2010 , Page(s): vii - x
    Request Permissions | PDF file iconPDF (96 KB)  
    Freely Available from IEEE
  • Conference inauguration speech

    Publication Year: 2010 , Page(s): xi
    Request Permissions | Click to expandAbstract | PDF file iconPDF (10 KB)  

    Provides an abstract of the invited presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Conference keynote addresses

    Publication Year: 2010 , Page(s): xii
    Request Permissions | Click to expandAbstract | PDF file iconPDF (42 KB) |  | HTML iconHTML  

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Conference invited talks

    Publication Year: 2010 , Page(s): xiii
    Request Permissions | Click to expandAbstract | PDF file iconPDF (41 KB) |  | HTML iconHTML  

    Provides an abstract for each of the invited presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Panel session: Challenges of Nano Electronics Industry Ecosystem in the Arab Region

    Publication Year: 2010 , Page(s): xiv
    Request Permissions | PDF file iconPDF (26 KB)  
    Freely Available from IEEE
  • Session 1.1: IC physical design & circuit design

    Publication Year: 2010 , Page(s): 1 - 2
    Request Permissions | PDF file iconPDF (18 KB)  
    Freely Available from IEEE
  • An automated design methodology for stress avoidance in analog & mixed signal designs

    Publication Year: 2010 , Page(s): 3 - 7
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1771 KB) |  | HTML iconHTML  

    Continuous scaling of CMOS devices in nm regime along with the complex processes result in increasing stress contribution in circuit performance that is no longer second order effect. Shallow Trench Isolation (STI) induced mechanical stress impacts analog designs dramatically, it is sufficient to shift bias point, change design parameters, and cause severe mismatch between transistors. This paper ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improving timing characteristics through Semi-Random Net Reordering

    Publication Year: 2010 , Page(s): 8 - 12
    Request Permissions | Click to expandAbstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    This work discusses the Semi-Random Net Reordering (SRNR) technique as a means to improve signal integrity and predictability of timing characteristics for wide signal busses. SRNR is able to reduce induced noise, signal propagation delay, signal transition speed, and their variations amongst the different wires comprising the bus. SRNR produces a faster routing structure that is more uniformly be... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs

    Publication Year: 2010 , Page(s): 13 - 17
    Request Permissions | Click to expandAbstract | PDF file iconPDF (870 KB) |  | HTML iconHTML  

    Lithography and stress variations are two dominant effects that significantly impact the functionality and performance of circuit designs at 45nm and below. Variability-aware circuit analysis methods have been introduced into the circuit design flow as one approach for implementing Design For Manufacturability (DFM) tools. These tools bridge the chip design implementation and manufacturing know-ho... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Voltage island design in multi-core SIMD processors

    Publication Year: 2010 , Page(s): 18 - 23
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1452 KB) |  | HTML iconHTML  

    Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay cha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High speed low power composite field SBOX

    Publication Year: 2010 , Page(s): 24 - 27
    Request Permissions | Click to expandAbstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    High speed and low power SBOX for Advanced Encryption Standard (AES) is proposed in this paper. Composite Galois Field is used in SBOX architecture to reduce size and delay of the circuit. Transmission gate is employed to reduce power consumption of the circuit. The proposed SBOX architecture consumes 186μw at 10MHz. The delay is reduced by 28.1%, and the average power consumption is reduce... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Blank page]

    Publication Year: 2010 , Page(s): 28
    Request Permissions | PDF file iconPDF (5 KB)  
    Freely Available from IEEE
  • Session 1.2: SOC, NOC, and application design

    Publication Year: 2010 , Page(s): 29 - 30
    Request Permissions | PDF file iconPDF (32 KB)  
    Freely Available from IEEE
  • Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm

    Publication Year: 2010 , Page(s): 31 - 36
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    In this paper, efficient hardware of one of the most popular encryption algorithms, the Advanced Encryption Standard (AES), is presented. A modified sub-pipelined structure is proposed targeting high speed and low power-delay product of the compact AES design with on-the-fly key expansion unit. By adding 25.8% in hardware complexity to the existing ASIC designs, the throughput is increased more th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and implementation of low latency network interface for network on chip

    Publication Year: 2010 , Page(s): 37 - 42
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (644 KB) |  | HTML iconHTML  

    The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Soft-core reduction methodology for SIMD architecture: OPENRISC case study

    Publication Year: 2010 , Page(s): 43 - 48
    Request Permissions | Click to expandAbstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of paralleli... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Blank page]

    Publication Year: 2010 , Page(s): 49 - 52
    Request Permissions | PDF file iconPDF (229 KB)  
    Freely Available from IEEE
  • [Blank page]

    Publication Year: 2010 , Page(s): 53 - 58
    Request Permissions | PDF file iconPDF (233 KB)  
    Freely Available from IEEE
  • Session 2.1: Fault tolerance & failure analysis

    Publication Year: 2010 , Page(s): 59 - 60
    Request Permissions | PDF file iconPDF (23 KB)  
    Freely Available from IEEE