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Electronic System Design (ISED), 2010 International Symposium on

Date 20-22 Dec. 2010

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  • [Front cover]

    Page(s): C1
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  • [Title page i]

    Page(s): i
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  • [Title page iii]

    Page(s): iii
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  • [Copyright notice]

    Page(s): iv
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  • Table of contents

    Page(s): v - ix
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  • Message from the General Chairs

    Page(s): x
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  • Message from the Technical Program Chairs

    Page(s): xi
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  • Organizing Committee

    Page(s): xii - xiii
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  • Program Committee

    Page(s): xiv - xv
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  • Additional reviewers

    Page(s): xvi
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  • Moore's Law and Beyond: Electronic Design Challenges

    Page(s): 1
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (67 KB) |  | HTML iconHTML  

    CMOS integrated circuit technology is expected to scale down for a few more technology nodes, enabling several billion transistors on a single chip. New technologies are now being explored as potential successors to CMOS. This talk will explore the challenges in electronic design, both with the next generations of CMOS technology and with potential new replacements. The challenges include high-level and hierarchical design approaches with abstractions for the building blocks to deal with the increasing complexities and new technologies. Designs need to trade off between performance and power. New techniques need to be developed to deal with the complexity of design verification and the problems of testing for subtle defects after manufacture. Other challenges include the need to deal with analog and RF blocks in a system, as well as the need to potentially include mechanical, chemical and biological elements for sensors. Finally, the question needs to be raised whether we are making the best use of the computational elements we have. View full abstract»

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  • Trends and Advances in Computing and Communication

    Page(s): 2
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    This talk will deal with the current trends and advances in Computing and Communication. The talk will highlight Intel's response to these trends. The areas of focus at Intel in connection to this trend will be discussed. The talk will discuss several challenges and opportunities that academics and advanced students can focus. It will set a roadmap for exploring solutions for these challenges. View full abstract»

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  • Rapid Emergence and Convergence of Electronic Technologies as Multiplying Factor for Innovation Capability

    Page(s): 3
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    This key note speech outlines the 4-Es related to electronic industry: 1. Explosion through multi-pronged fundamental research in materials etc, has significantly contributed towards efficient, cost-effective and small-in-size electronic systems. 2. Emergence of new technological domains like molecular (micro & nano) electronics which are seeing huge application potential. 3. End-use of these technologies across industries in the today's scenario. 4. Extrapolation towards future technologies for 2050! View full abstract»

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  • Pin-Constrained Designs of Digital Microfluidic Biochips for High-Throughput Bioassays

    Page(s): 4 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    Digital microfluidic(DMF) biochips have emerged recently as a viable platform of implementing conventional laboratory-based biochemical procedures. These tiny chips are able to manipulate nanoliter volume of discrete fluid dropletson an electrode array via electrical actuation. However, with the increasing dimension of the array, the number of external control pins connected to the electrodes may increase significantly. Several pin-constrained biochip design techniques have been proposed earlier for controlling the electrodes through a small number of pins, a short review of which is presented in this paper. An important design problem in such a chip is interconnection wire routing for the identically controlled electrodes. To address this problem, we propose a new scheme of layered wire routing for a special class of pin-constrained biochips that can concurrently execute multiple instances of the same bioassay to increase throughput. We also describe a hierarchical routing scheme to ensure scalability. View full abstract»

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  • Introducing Energy Efficiency into Graphics Processors

    Page(s): 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB) |  | HTML iconHTML  

    Graphics processor (GPU) architectures have evolved rapidly in recent years with increasing performance demanded by 3D graphics applications such as games. However, challenges exist in integrating complex GPUs into mobile devices because of power and energy constraints, motivating the need for energy efficiency in GPUs. While a significant amount of power optimisation research effort has concentrated on the CPU system, GPU power efficiency is a relatively new and important area because the power consumed by GPUs is similar in magnitude to CPU power. Power and energy efficiency can be introduced into GPUs at many different levels: 1) Hardware component level - queue structures, caches, filter arithmetic units, interconnection networks, processor cores, etc., can be optimised for power. 2) Algorithm level - the deep and complex graphics processing computation pipeline can be modified to be energy aware. Shader programs written by the user can be transformed to be energy aware. 3) System level - co-ordination at the level of task allocation, voltage and frequency scaling, etc., requires knowledge and control of several different GPU system components We outline two strategies for applying energy optimisations at different levels of granularity in a GPU: (1) Texture Filter Memory (TFM) - an energy-efficient addition to the texture memory hierarchy component; and (2) an overall system level Dynamic Voltage and Frequency Scaling (DVFS) based energy reduction strategy based on an accurate tile-level slack prediction. Texture Filter Memory is an augmentation of the standard GPU texture cache hierarchy. Instead of a regular data cache hierarchy, we employ a small first level register based structure that is optimised for the relatively predictable memory access stream in the texture filtering computation. Predictability of the memory access patterns leads us to reduce power by using a simpler register access structure. Power is saved by avoiding the expensive tag lookup and - - comparisons present in regular caches. Further, the texture filter memory is a very small structure, whose access energy is much smaller than a data cache of similar performance. Dynamic Voltage and Frequency Scaling, an established energy management technique, can be applied in GPUs by first predicting the workload in a given frame, and, where sufficient slack exists, lowering the voltage and frequency levels so as to save energy while still completing the work within the frame rendering deadline. We apply DVFS in a tiled graphics renderer, where the workload prediction and voltage/frequency adjustment is performed at a tile-level of granularity, which creates opportunities for on-the-fly correction of prediction inaccuracies, ensuring high frame rates while still delivering low power. Tile-level energy management schemes are distinctly superior to schemes that work at the granularity of the entire frame in terms of energy saving and quality of the rendering measured in terms of frames rendered per second. The prediction mechanism relies both on the history - workload observed for the tile in recent frames, as well as rank - a quantification of the tile workload based on the frame structure, consisting of geometry, pixel shading, texture, and raster operations workloads. View full abstract»

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  • Design and Validation of Robust Systems

    Page(s): 11 - 13
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    Robust system design ensures that future electronic systems perform correctly despite increasing complexity and rising levels of disturbances in the underlying hardware. This paper discusses two essential aspects of robust system design. View full abstract»

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  • Skip the Analysis: Self-Optimising Networks-on-Chip (Invited Paper)

    Page(s): 14 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (673 KB) |  | HTML iconHTML  

    In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self-optimising NoC topology: Skip-links, which inserts long-range links into a standard mesh. We evaluate the performance of Skip-links at run-time against the optimal configuration, as determined by static analysis, for both the transpose and tornado traffic patterns. We show that the local decision-making algorithm employed by Skip-links comes close to optimum, carrying 70% of theoretical maximum traffic flows for tornado traffic, and reducing average hop counts by 18% for transpose traffic. View full abstract»

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  • A Practitioner's Approach to Software System Design

    Page(s): 20 - 23
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    How to design an efficient and cost effective software system is a million dollar question to every software engineer. The challenges lie in the fact that there is no such fixed rules and regulations, following which will produce an efficient software system. Practitioners have proposed many solutions to address this issue. In this discussion, we will try to touch base on some of the vital points which a practitioner is encouraged to adapt in order to lead a team of software engineers to produce cost effective efficient system. View full abstract»

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  • History and Trends in Analog Circuit Challenges at the System Level

    Page(s): 24
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    In contemporary systems much of the system is embodied in the silicon components. A good example is Intel's Huron River mobile platform, comprising the Sandy Bridge microprocessor and Cougar Point PCH (Platform Controller Hub). The microprocessor component contains up to four CPU cores, an integrated memory controller supporting dual-channel DDR3, PCIe Generation 2, and integrated graphics. The SATA, USB, and display interfaces reside in the PCH component. Both the microprocessor and PCH components represent significant complexity, not only from a logic point of view, but also from an analog circuit point of view. Contemporary platform signaling speeds include up to 1600 Mb/s single-ended DDR3 and 5 Gb/s differential PCIe Gen2. The typical circuit board material in systems has limitations that require analog complexity to overcome the limits. The risk for post-Si bugs in these circuits is proportional to the circuit complexity. Complicating this is the need to conserve both power and silicon die area: both challenging to the analog circuit designer, and both adding to the overall design complexity. One other factor affecting analog circuitry is in the mixed signal domain, seen primarily in the timing convergence domain. Interfaces - whether single-ended memory channels or differential PCIe channels - are governed by strict clocking and timing budgets. As the signaling speed increases, the clock and timing budgets continue to shrink. This also fuels the risk of circuit bugs. This talk will examine the history and trends of analog and circuit issues that have evolved as system-level integration has been increasing. View full abstract»

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  • Using Test and Diagnosis to Enable Tomorrow's Robust Systems

    Page(s): 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (78 KB) |  | HTML iconHTML  

    Producing reliable, integrated systems is becoming extremely difficult due to the increasing variability and uncertainty inherent in advancing fabrication technologies; the worsening effects of various wear-out mechanisms; and environmental disturbances (e.g., soft errors due to radiation). Solutions to this problem centering on traditional approaches involving redundant resources are likely to be impractical due to the negative impact on power and performance. Because of this trend, it is widely believed that approaches for enabling chips to self-X (where X = monitor, diagnose, calibrate, compensate, heal, etc.) will be needed to ensure reliable operation over a chip's expected lifetime. In collaboration with Prof. Mitra of Stanford University, our work in this area is focused on developing methodologies that enable integrated systems to self-monitor, self-diagnose, and self-compensate for various non-idealities. In this talk, I will describe how state-of-the-art diagnosis of failing ICs today is used today to extract valuable information about design, manufacturing and test itself. Although tremendously beneficial, a fault simulator, significant amounts of design data, and powerful computer servers are needed to perform diagnosis. It is therefore infeasible to implement traditional effect-cause diagnosis within a system. We are therefore developing efficient cause-effect (i.e., fault dictionary) based approaches for performing in-system diagnosis. I will conclude the talk by describing approaches for developing efficient fault dictionaries for on-chip implementation. View full abstract»

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  • Power Management in Multi-source Environment

    Page(s): 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB) |  | HTML iconHTML  

    Summary form only given. Power management has become ubiquitous with the proliferation of computing and communication gadgets in our daily life. The wrist-watch, the mobile phone, the notebook computer, all require power in various form and need to have a proper management of the same to ensure availability, efficiency and environment-friendliness. The focus is therefore to exploit multiple sources of energy, be it an ac-line outlet, battery, solar insolation, fuel-cells and even from body heat and vibrations. We are trying to scavenge every iota of energy from our environment in order to reduce the need for “external” sources like the ac line and also reduce the clutter of wires associated with them. This makes it quite attractive from the consumer's point of view. However, at the same time, this is introducing new challenges to the designers of the power management systems. They have the task of integrating power from multiple sources, each with a variable degree of availability, and make it available in an efficient way to the point of load. New topologies and control methodologies are therefore becoming necessary to achieve these objectives. This talk will first describe the current and future scenarios of power management and then go on to discuss some of the promising architectures that are likely to be successful in achieving the objectives outlined above. View full abstract»

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  • Timing Analysis in Carbon Nanotube Interconnects with Process, Temperature, and Voltage Variations

    Page(s): 27 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (450 KB) |  | HTML iconHTML  

    Carbon Nanotube (CNT) based interconnect has become the most promising replacement for Cu based interconnect in future VLSI technology in the nanometer regime. In this work, we compare the performance of copper (Cu) and CNT based interconnect for four ITRS technology nodes. We also analyze the timing delay in CNT based interconnect under different process, temperature, and voltage (PTV) corners for 32 nm technology node. The equivalent circuit model for CNT based interconnect has been developed. It is found that CNT based interconnect performs better for long interconnects as compared to Cu wire. The performance varies by more 50% with process variation where as with voltage and temperature the delay variations are ~3% and ~13-23% from the nominal voltage and room temperature, respectively. View full abstract»

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  • CMOS LC Voltage-Controlled Oscillator Design Using Multiwalled Carbon Nanotube Wire Inductor

    Page(s): 33 - 37
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    A new CMOS LC voltage-controlled oscillator (VCO) circuit design using multiwalled carbon nanotube (MWCNT) wire inductor in LC tank circuit is presented. The VCO is designed in TSMC 0.18 μm CMOS process. We have applied our recently reported one-dimensional fluid electronic transport model of multiwalled carbon nanotube interconnect in π-model of the inductor. We have studied the oscillation frequency and phase noise of CMOS LC VCO and compared the performance using MWCNT and Cu wire inductors as a function of the quality factor (Q). We have shown that the oscillation frequency of the CMOS LC VCO is increased due to high-Q of MWCNT wire inductor. We have also shown that the phase noise performance of VCO designed with MWCNT wire inductor is also considerably improved in comparison to that of VCO designed with conventional Cu wire inductor. View full abstract»

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  • Design of a Coffee Vending Machine Using Single Electron Devices: (An Example of Sequential Circuit Design)

    Page(s): 38 - 43
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    In this paper we propose an implementation technique for sequential circuit using single electron tunneling technology (SET-s) with the example of designing of a “coffee vending machine” with the goal of getting low power and faster operation. We implement the proposed design based on single electron encoded logic (SEEL).The circuit is tested and compared with the existing CMOS technology. View full abstract»

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  • Retail Beamed Power for a Micro Renewable Energy Architecture: Survey

    Page(s): 44 - 49
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    Retail delivery of electric power through millimeter waves is relevant in developing areas where the market for micro devices outpaces the power grid infrastructure. It is also a critical component of an evolutionary path towards terrestrial and space-based renewable power generation. Narrow-band power can be delivered as focused beams to receivers near end-users, from central power plants, rural distribution points, UAVs, stratospheric airship platforms or space satellites. The paper surveys the available knowledge base on millimeter wave beamed power delivery. It then considers design requirements for a retail beamed power architecture, in the context of rural India where power delivery is lagging behind the rapid rise in demand for micro-drives and connectivity. View full abstract»

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