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Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian

Date 8-10 Nov. 2010

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Displaying Results 1 - 25 of 104
  • A low data rate FM-UWB transmitter with-based sub-carrier modulation and quasi-continuous frequency-locked loop

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (661 KB) |  | HTML iconHTML  

    This paper describes the architecture and circuit design of a low data rate FM-UWB transmitter. A Δ-Σ fractional-N PLL with a multi-phase relaxation oscillator is designed to enable sub-carrier modulation with reduced quantization noise. The triangular waveform output of the relaxation oscillator directly modulates an LC VCO to have the UWB-compliant spectrum. The center frequency of the LC VCO is quasi-continuously tuned by a Δ-Σ DAC based frequency-locked loop with the power consumption of 1.1mW. The 3.43-4.03GHz FM-UWB transmitter implemented in 0.18μm CMOS consumes the total power of 9.6mW. View full abstract»

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  • A 5.9mW 50Mbps CMOS QPSK/O-QPSK transmitter employing injection locking for direct modulation

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (916 KB) |  | HTML iconHTML  

    900MHz QPSK/O-QPSK transmitter suitable for biomedical high quality imaging application is presented. The phase modulation is achieved by directly modifying the self-resonant frequency of a sub-harmonic injection-locked oscillator through capacitor bank switching. Due to the simplicity of the proposed architecture, implemented in 0.18μm CMOS technology, it consumes very low power of 3mW and 5.88mW with 1.2V and 1.4V supply voltages respectively, while transmitting at 50Mbps data rate. The transmitter can deliver output power of -3.3dBm at 1.4V supply with an EVM of 6.6%. View full abstract»

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  • A 18 mW Tx, 22 mW Rx transceiver for 2.45 GHz IEEE 802.15.4 WPAN in 0.18-µm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (921 KB) |  | HTML iconHTML  

    This paper demonstrates a highly integrated transceiver for 802.15.4, consuming a dc power of 18 mW and 22.3 mW in the Tx and Rx mode respectively. The gm boosted LNA shares the dc current with mixer, complex filter uses transistorized biquads, Limiting Amplifier and RSSI chain uses two local loops to save dc power. In the Tx, 2-point direct FSK modulation using normal sized varactors are used in the PLL, which not only obviates the need for auto calibration but also saves dc power due to the absence of DAC. The low IF receiver achieves a sensitivity of -94 dBm, an over load point of -20 dBm adjacent and alternate channel rejections of 40 dB and 55 dB respectively and a linear RSSI range of 89 dB. The transmitter delivers an OQPSK modulated signal of 0 dBm, with an EVM of 7% and the output spectrum meets the mask requirements of 802.15.4, FCC & ETSI. Implemented in 0.18-μm CMOS, loop filter and the crystal resonator for the PLL are the only external components apart from the decoupling capacitors. View full abstract»

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  • A linearity improvement technique for a class-AB CMOS Power Amplifier with a direct feedback path

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB) |  | HTML iconHTML  

    A new linearity improvement technique is introduced for a class-AB CMOS Power Amplifier (PA). The proposed PA has two stages and each stage has a cascode configuration. A direct feedback path from the input of the power stage to the input of the driver stage via an Accumulation-mode MOS (AMOS) varactor is adopted to improve the linearity. This additional path provides a negative feedback loop for the second-order harmonic, and the AMOS varactor controls the loop gain and the amount of the phase shift of the feedback signals. The proposed PA has been implemented in a standard 0.18-μm CMOS technology. The measured results show a gain of 21.4 dB, a maximum output power of 23.5 dBm with 43.1 % of peak Power-Added-Efficiency (PAE), and a linear output power of 21.4 dBm with 40 % PAE using a 1.85 GHz single tone. The two-tone test demonstrates 10 dBc improvement in the third-order Intermodulation Distortion (IMD3) compared to a conventional PA. View full abstract»

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  • An antenna mismatch immuned CMOS power amplifier

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB) |  | HTML iconHTML  

    A 2.4 GHz reconfigurable CMOS power amplifier to minimize antenna mismatch effects is presented. The PA is implemented by using a 0.18-μm RF CMOS process, and the supply voltage is 3.3 V. The proposed PA is compared to a conventional PA with a fixed matching network. By utilizing the proposed reconfigurable matching network, both the efficiency and the output power are improved under an antenna mismatch condition while satisfying the linearity specifications. For example, the maximum linear power and PAE are increased from 11.1-dBm to 16.1-dBm and from 8.1% to 19% at a Γ=0.3<;45 condition, respectively. To our knowledge, this is the first fully-integrated CMOS PA with a reconfigurable matching network that improves the robustness to the antenna mismatch. View full abstract»

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  • A CMOS MedRadio receiver RF front-end with complementary current-reuse LNA for biomedical applications

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (182 KB) |  | HTML iconHTML  

    An ultra-low-power 401-406 MHz Medical Device Radiocommunication Service (MedRadio) receiver RF front-end for biomédical telemetry applications is implemented using 0.18-μm CMOS technology with a 1-V supply voltage. The receiver RF front-end employs the proposed complementary current-reuse low-noise amplifier (CCRLNA) which shows enhanced noise and linearity performance in comparison to the well-known source degeneration cascode LNA at equal power consumption and design conditions. The RF front-end including the proposed CCRLNA, transconductor, I/Q folded mixer, and LO buffers achieves a conversion gain of 28.7 dB, NF of 5.5 dB, and IIP3 of -25 dBm while consuming less than 500μ W from a 1-V supply voltage and occupying 0.7mm2 of core die area. View full abstract»

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  • Zero-crossing detector based reconfigurable analog system

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92mW at 50MSPS with ENOB of 8.02b and FOM of 150fJ/conversion-step. A third order Butterworth filter is also demonstrated. The chip is implemented in 65nm technology. View full abstract»

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  • Parasitic discrete-time-pole cancelling techniques for ultra-wideband discrete-time charge-domain baseband filters

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    Parasitic discrete-time-pole cancelling techniques that use a discrete-time IIR BPF are presented. Parasitic capacitors, which usually cause undesirable lowpass parasitic discrete-time poles in ultra-wideband applications, are utilized to provide bandpass parasitic discrete-time poles, thus improving the frequency characteristics in parallel with passband equalizer circuits. A novel charge transfer scheme that reduces the parasitic sensitivity of the output nodes is also implemented. The prototype filter has been implemented with a 90 nm CMOS technology. Measurements show that a 250-MHz cutoff, 0-db gain discrete-time charge-domain filter and an 8-phase clock pulse generator dissipate 8 mA and 1 mA, respectively, from a 1.2-V supply voltage. View full abstract»

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  • A cascade non-decimation charge-domain filter with noise-folding reduction

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (743 KB) |  | HTML iconHTML  

    A cascade non-decimation charge-domain filter (CNCDF) with noise-folding reduction for high attenuation and bandwidth was proposed. The CNCDF, based on non-decimation property, could suppress the noise-folding source from a down-sampling rate and duplicate-sampled signals upon a sensible input-clock rate (ICR). By using 600-MS/s ICR, the measurement showed 91-dB attenuation of the first folding signal, 95-dB stop-band attenuation, and 10-MHz bandwidth. The chip also possessed 30-dB gain and 6-dBm IIP3, consuming 11.86-mA current from a 1.2-V power supply. The chip, including ESD and clock-logical circuits, occupies 3.6 mm2 in 90-nm CMOS process. View full abstract»

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  • A 2.3mA 240-to-500MHz 6th-order active-RC low-pass filter for ultra-wideband transceiver

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    This paper presents a 6th-order active-RC low-pass filter with 240 MHz to 500 MHz tunable bandwidth, which is suitable for the ultra-wideband transceivers. The filter consumes only 2.3 mA from 1.8 V supply voltage, which is mainly attributed to the proposed highly power-efficient operational amplifier (Opamp) with an adaptive-biased pole-cancellation push-pull source follower as the buffer stage to drastically extend the bandwidth. The technique of high-frequency common-mode rejection using parasitic capacitor is utilized to guarantee the Opamp stability. In addition, the filter adopts the Q-tuning technique and Opamp GBW compensation mechanism, which relax the GBW requirement of the Opamp to further reduce the power consumption. The filter achieves 1.36 pW/pole/Hz normalized power, 13.1 nVA√Hz input-referred noise density, 15.9 dBm in-band IIP3, and 34 dBm out-of-band IIP3, respectively. The chip is fabricated in a standard 0.18 μm CMOS process, and occupies 0.23 mm2 silicon area without pads. View full abstract»

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  • A 70–280 MHz frequency and Q tunable 53 dB SFDR Gm-C filter for ultra-wideband

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (553 KB) |  | HTML iconHTML  

    A 70-280 MHz 5th-order Chebyshev Gm-C low-pass filter was implemented in 0.13μm CMOS process to support both WiMedia UWB and lower rate IR-UWB applications. The filter response is accurately maintained over 4× frequency range by using unit Gm cell arrays and independent Q tuning circuit. To improve linearity of Gm-C filter in low supply voltage, a modified LC ladder topology is proposed. The IIP3 performance is improved more than 10 dB compared to conventional Gm-C filter. A measured spurious free dynamic range (SFDR) of more than 50 dB is maintained when the filter cut-off frequency is programmed. It occupies an area of 0.12 mm2 and consumes 21 mW under supply of 1.5 V. View full abstract»

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  • Clocked comparator for high-speed applications in 65nm technology

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement and simulation results show that the proposed design has an average of 31% higher speed and ~17% less active area than the conventional design. View full abstract»

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  • A 120-GHz transmitter and receiver chipset with 9-Gbps data rate using 65-nm CMOS technology

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (715 KB) |  | HTML iconHTML  

    The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9. View full abstract»

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  • 130-GHz gain-enhanced SiGe low noise amplifier

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    A 130 GHz low noise amplifier (LNA) in 0.13-μm SiGe BiCMOS technology has been designed and characterized. The gain-boosted cascode topology with 3D grounded-shielding structures is employed. The results showed that the LNA with a chip area of 400 μm × 900 μm, gain of ~17.5 dB with a 3-dB bandwidth of ~25 GHz, and noise figure of ~7.7 dB at 130 GHz with total dc power consumption of 31.5 mW has demonstrated. View full abstract»

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  • A 63 GHz low-noise active balun with broadband phase-correction technique in 90 nm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (187 KB) |  | HTML iconHTML  

    This paper presents a low-noise active balun with broadband phase-correction. The proposed phase-correction structure is independent of operation frequency, and effectively suppresses phase deviation of active balun at millimeter-wave (MMW) band. Within the low noise current-reuse pre-amplifier, this active balun circuit can be employed as low-noise amplifier as well. This circuit is fabricated in 90nm low power CMOS technology with core area of 0.275 mm2. The measured phase error is less than 10 degrees from 50 GHz to 67 GHz, which demonstrates the robust calibration of phase error at MMW frequency. The measured voltage gain and noise figure at 63 GHz are 17.6 dB and 8.6 dB, respectively. The measured IIP3 is around -7 dBm. The core power consumption is 19 mW from 1.4 V supply voltage. View full abstract»

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  • A 60 GHz heterodyne quadrature transmitter with a new simplified architecture in 90nm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (494 KB) |  | HTML iconHTML  

    A 60 GHz heterodyne up-convertor consuming only 29 mW, together with a PA consuming 84 mW, is presented. It is implemented in 90 nm CMOS. It takes advantage of sub-harmonic mixing and a sliding IF architecture, using a single LO around the relatively low frequency of 20 GHz, thus relaxing millimeter-wave LO design. This also allowed LO buffers to be eliminated, which minimizes area and power consumption. The I/Q up-converter includes a quadrature VCO, resistive IF mixers, IF amplifier and RF sub-harmonic mixer. It achieves a tuning range of 8.8 % and a conversion gain of 13.1 dB. The 60 GHz power amplifier delivers 9.8 dBm, has 9.7 % PAE and 20 dB gain. View full abstract»

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  • A compact, fully differential D-band CMOS amplifier in 65nm CMOS

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    A fully differential 144GHz CMOS amplifier has been demonstrated in 65nm CMOS. It validates a maximum 20dB power gain and has positive gain over 38GHz frequency range from 126GHz to 164GHz. With stacking circuit architecture, the amplifier can tolerate up to 2V supply without reliability concern. It also delivers over 5.7dBm saturated output power with PldB of 5dBm under a 2V supply. The amplifier features a 3-stage common-source cascode architecture with on-chip interstage matching. The chip occupies 0.05 mm2 area and draws 39mA and 51mA from 1.4V and 2V supplies respectively. To our best knowledge, this amplifier achieves the highest power gain for CMOS amplifier beyond 100GHz and paves the way for D-band radar and passive imaging system applications. View full abstract»

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  • 0.6V voltage doubler and clocked comparator for correlation-based impulse radio UWB receiver in 65nm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (826 KB) |  | HTML iconHTML  

    This paper presents a 0.6-V voltage doubler and a 0.6-V clocked comparator in 65 nm CMOS. For the multi-phase sampling application, such as charge-domain correlator for impulse UWB receivers or analog-to-digital converter, the proposed voltage doubler can reduce the power consumption and the chip area by half compared to the conventional one. The non-overlapping complementary clock generator used in the conventional voltage doubler can be eliminated by simply swapping the input clock order in the voltage doubler. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the proposed voltage booster. View full abstract»

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  • A 92m W 76.8GOPS vector matching processor with parallel Huffman decoder and query re-ordering buffer for real-time object recognition

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    A vector matching processor with memory bandwidth optimizations is proposed to achieve real-time matching of 128 dimensional SIFT features extracted from VGA video. The main bottleneck of feature-vector matching is the off-chip database access. We employ the locality sensitive hashing (LSH) algorithm which reduces the number of database comparisons required to match each query. In addition, database compression using Huffman coding increases the effective external bandwidth. Dedicated parallel Huffman decoder hardware ensures fast decompression of the database. A flexible query re-ordering buffer exploits overlapping accesses between queries by enabling out-of-order query processing to minimize redundant off-chip access. As a result, the 76.8 GOPS feature matching processor implemented in a 0.13um CMOS process achieves 43200 queries/second on a 100 object database while consuming peak power of 92mW. View full abstract»

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  • A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79 Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7 Gbps/mm2 and 62.4pJ/bit, respectively. View full abstract»

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  • A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90 nm CMOS ASIC has a core area of 1.77 mm2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8pJ/bit/iteration at a nominal operating voltage of 1.0 V. View full abstract»

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  • A 5.35 mm2 10GBASE-T Ethernet LDPC decoder chip in 90 nm CMOS

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 100BASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up the convergence of the message passing decoding algorithm. To avoid routing congestion the decoder architecture employs a novel communication scheme that reduces the critical number of global wires by 50%. The prototype LDPC decoder ASIC, fabricated in 90 nm CMOS, occupies only 5.35 mm2 and achieves a decoding throughput of 11.69 Gb/s at 1.2 V with an energy efficiency of 133pJ/bit. View full abstract»

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  • A 2×2–8×8 sorted QR decomposition processor for MIMO detection

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    Due to the growing demand of transmission capacity of the wireless communication system, multiple-input multiple-output orthogonal-frequency-division-multiplexing (MIMO-OFDM) communication system requires more and more MIMO antennas and a large number of OFDM subcarriers. Thus, the QR decomposition becomes one of the computational bottlenecks in the QR-based MIMO detection. The proposed Givens-Rotation-based QR decomposition algorithm features efficient parallel processing with sorting function that resolves the trade-off between the detection performance and hardware utilization efficiency. According to the algorithm, we designed and implemented a 2 × 2 ~ 8 × 8 QR decomposition processor using TSMC 0.18μm 1P6M CMOS technology. The throughput of the QR decomposition processor achieves 6.8×104 SQRD per second, which outperforms other works in the literature after being normalized by the MIMO dimension. View full abstract»

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  • A low-complexity heterogeneous multi-core platform for security soc

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    This paper presents a heterogeneous multi-core SoC platform to deal with intensive cryptography algorithms in different security protocols. And several cores are integrated in the proposed Platform, which are a MlPS-like general processor (GP), a dedicated package processor (PP) for fast data package, and multiple security processors (SP) for cryptography. The low-cost dedicated SPs can execute cryptography algorithms flexibly and efficiently, and the processing performance of this platform can be enhanced easily by exploiting algorithms parallelism on multiple cores. Moreover, a test chip is implemented in SEVIC 0.13μm standard CMOS technology, and its functionality and performance are well verified. It can achieve 565Mbps, 256Mbps, 19Kbps, and 16Kbps throughput for AES(128), SHA-1, RSA(1024), ECC(p192) respectively. Comparison results shows that it also has a low-complexity hardware cost but more flexibility. View full abstract»

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  • A 2-Gb/s 5.6-mW digital equalizer for a LOS/NLOS receiver in the 60GHz band

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation is beneficial for efficient transmitter and receiver implementation. Equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions based on the IEEE WPAN standard. Power consumption is minimized by using parallelized distributed arithmetic (DA). A 2 mm × 2 mm test chip in 65 nm CMOS implements a 6-tap feedforward and 32-tap feedback equalizer that consumes 5.6 mW at 2.0 Gb/s throughput. View full abstract»

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